| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 42 if (getOpcode() < ISD::BUILTIN_OP_END)
60 case ISD::DELETED_NODE: return "<<Deleted Node!>>";
62 case ISD::PREFETCH: return "Prefetch";
63 case ISD::ATOMIC_FENCE: return "AtomicFence";
64 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap";
65 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: return "AtomicCmpSwapWithSuccess";
66 case ISD::ATOMIC_SWAP: return "AtomicSwap";
67 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd";
68 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub";
69 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd"
[all...] |
| LegalizeVectorOps.cpp | 15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
202 if (Op.getOpcode() == ISD::LOAD) {
204 ISD::LoadExtType ExtType = LD->getExtensionType();
205 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD)
230 } else if (Op.getOpcode() == ISD::STORE) {
248 } else if (Op.getOpcode() == ISD::MSCATTER || Op.getOpcode() == ISD::MSTORE
[all...] |
| LegalizeIntegerTypes.cpp | 52 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
53 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
54 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
55 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
56 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break;
57 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
58 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
59 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
60 case ISD::CONVERT_RNDSAT:
62 case ISD::CTLZ_ZERO_UNDEF
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 95 int ISD = TLI->InstructionOpcodeToISD(Opcode);
96 assert(ISD && "Invalid opcode");
98 if (ISD == ISD::SDIV &&
119 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle.
121 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence
122 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence
123 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence
124 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence
129 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD,
[all...] |
| /external/llvm/include/llvm/Target/ |
| CostTable.h | 25 int ISD;
32 int ISD, MVT Ty) {
35 return ISD == Entry.ISD && Ty == Entry.Type; });
45 int ISD;
55 int ISD, MVT Dst, MVT Src) {
58 return ISD == Entry.ISD && Src == Entry.Src &&
|
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/Target/ |
| CostTable.h | 26 int ISD;
33 int ISD, MVT Ty) {
35 return ISD == Entry.ISD && Ty == Entry.Type;
46 int ISD;
56 int ISD, MVT Dst, MVT Src) {
58 return ISD == Entry.ISD && Src == Entry.Src && Dst == Entry.Dst;
|
| /prebuilts/clang/host/darwin-x86/clang-4393122/include/llvm/Target/ |
| CostTable.h | 26 int ISD;
33 int ISD, MVT Ty) {
35 return ISD == Entry.ISD && Ty == Entry.Type;
46 int ISD;
56 int ISD, MVT Dst, MVT Src) {
58 return ISD == Entry.ISD && Src == Entry.Src && Dst == Entry.Dst;
|
| /prebuilts/clang/host/darwin-x86/clang-4479392/include/llvm/Target/ |
| CostTable.h | 26 int ISD;
33 int ISD, MVT Ty) {
35 return ISD == Entry.ISD && Ty == Entry.Type;
46 int ISD;
56 int ISD, MVT Dst, MVT Src) {
58 return ISD == Entry.ISD && Src == Entry.Src && Dst == Entry.Dst;
|
| /prebuilts/clang/host/darwin-x86/clang-4579689/include/llvm/Target/ |
| CostTable.h | 26 int ISD;
33 int ISD, MVT Ty) {
35 return ISD == Entry.ISD && Ty == Entry.Type;
46 int ISD;
56 int ISD, MVT Dst, MVT Src) {
58 return ISD == Entry.ISD && Src == Entry.Src && Dst == Entry.Dst;
|
| /prebuilts/clang/host/darwin-x86/clang-4630689/include/llvm/Target/ |
| CostTable.h | 26 int ISD;
33 int ISD, MVT Ty) {
35 return ISD == Entry.ISD && Ty == Entry.Type;
46 int ISD;
56 int ISD, MVT Dst, MVT Src) {
58 return ISD == Entry.ISD && Src == Entry.Src && Dst == Entry.Dst;
|
| /prebuilts/clang/host/darwin-x86/clang-4639204/include/llvm/Target/ |
| CostTable.h | 26 int ISD;
33 int ISD, MVT Ty) {
35 return ISD == Entry.ISD && Ty == Entry.Type;
46 int ISD;
56 int ISD, MVT Dst, MVT Src) {
58 return ISD == Entry.ISD && Src == Entry.Src && Dst == Entry.Dst;
|
| /prebuilts/clang/host/darwin-x86/clang-4691093/include/llvm/Target/ |
| CostTable.h | 26 int ISD;
33 int ISD, MVT Ty) {
35 return ISD == Entry.ISD && Ty == Entry.Type;
46 int ISD;
56 int ISD, MVT Dst, MVT Src) {
58 return ISD == Entry.ISD && Src == Entry.Src && Dst == Entry.Dst;
|
| /prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/Target/ |
| CostTable.h | 26 int ISD;
33 int ISD, MVT Ty) {
35 return ISD == Entry.ISD && Ty == Entry.Type;
46 int ISD;
56 int ISD, MVT Dst, MVT Src) {
58 return ISD == Entry.ISD && Src == Entry.Src && Dst == Entry.Dst;
|
| /prebuilts/clang/host/linux-x86/clang-4393122/include/llvm/Target/ |
| CostTable.h | 26 int ISD;
33 int ISD, MVT Ty) {
35 return ISD == Entry.ISD && Ty == Entry.Type;
46 int ISD;
56 int ISD, MVT Dst, MVT Src) {
58 return ISD == Entry.ISD && Src == Entry.Src && Dst == Entry.Dst;
|
| /prebuilts/clang/host/linux-x86/clang-4479392/include/llvm/Target/ |
| CostTable.h | 26 int ISD;
33 int ISD, MVT Ty) {
35 return ISD == Entry.ISD && Ty == Entry.Type;
46 int ISD;
56 int ISD, MVT Dst, MVT Src) {
58 return ISD == Entry.ISD && Src == Entry.Src && Dst == Entry.Dst;
|
| /prebuilts/clang/host/linux-x86/clang-4579689/include/llvm/Target/ |
| CostTable.h | 26 int ISD;
33 int ISD, MVT Ty) {
35 return ISD == Entry.ISD && Ty == Entry.Type;
46 int ISD;
56 int ISD, MVT Dst, MVT Src) {
58 return ISD == Entry.ISD && Src == Entry.Src && Dst == Entry.Dst;
|
| /prebuilts/clang/host/linux-x86/clang-4630689/include/llvm/Target/ |
| CostTable.h | 26 int ISD;
33 int ISD, MVT Ty) {
35 return ISD == Entry.ISD && Ty == Entry.Type;
46 int ISD;
56 int ISD, MVT Dst, MVT Src) {
58 return ISD == Entry.ISD && Src == Entry.Src && Dst == Entry.Dst;
|
| /prebuilts/clang/host/linux-x86/clang-4639204/include/llvm/Target/ |
| CostTable.h | 26 int ISD;
33 int ISD, MVT Ty) {
35 return ISD == Entry.ISD && Ty == Entry.Type;
46 int ISD;
56 int ISD, MVT Dst, MVT Src) {
58 return ISD == Entry.ISD && Src == Entry.Src && Dst == Entry.Dst;
|
| /prebuilts/clang/host/linux-x86/clang-4691093/include/llvm/Target/ |
| CostTable.h | 26 int ISD;
33 int ISD, MVT Ty) {
35 return ISD == Entry.ISD && Ty == Entry.Type;
46 int ISD;
56 int ISD, MVT Dst, MVT Src) {
58 return ISD == Entry.ISD && Src == Entry.Src && Dst == Entry.Dst;
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
139 case ISD::ADD:
140 case ISD::SUB:
141 case ISD::MUL:
142 case ISD::SDIV:
143 case ISD::UDIV:
144 case ISD::SREM
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 77 int ISD = TLI->InstructionOpcodeToISD(Opcode);
78 assert(ISD && "Invalid opcode");
83 { ISD::FP_ROUND, MVT::v2f64, 2 },
84 { ISD::FP_EXTEND, MVT::v2f32, 2 },
85 { ISD::FP_EXTEND, MVT::v4f32, 4 }
88 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND ||
89 ISD == ISD::FP_EXTEND)) {
91 if (const auto *Entry = CostTableLookup(NEONFltDblTbl, ISD, LT.second)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCCallingConv.h | 24 CCValAssign::LocInfo &, ISD::ArgFlagsTy &,
|
| /external/llvm/lib/Target/Lanai/ |
| LanaiAluCode.h | 119 inline static AluCode isdToLanaiAluCode(ISD::NodeType Node_type) {
121 case ISD::ADD:
123 case ISD::ADDE:
125 case ISD::SUB:
127 case ISD::SUBE:
129 case ISD::AND:
131 case ISD::OR:
133 case ISD::XOR:
135 case ISD::SHL:
137 case ISD::SRL
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| Analysis.cpp | 147 /// getFCmpCondCode - Return the ISD condition code corresponding to
151 ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) {
152 ISD::CondCode FPC, FOC;
154 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
155 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
156 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
157 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 63 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
64 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
65 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
67 setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Expand);
68 setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Expand);
69 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
71 setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Expand);
72 setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Expand);
73 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
86 setOperationAction(ISD::BR_JT, MVT::Other, Expand)
[all...] |
