| /external/swiftshader/third_party/subzero/pydir/ |
| gen_arm32_reg_tables.py | 20 IsFP32=0, IsFP64=0, IsVec128=0, Aliases=None):
24 assert not (IsFP32 and IsFP64)
26 assert not (IsFP64 and IsVec128)
27 assert not ((IsGPR) and (IsFP32 or IsFP64 or IsVec128))
54 'IsFP32', 'IsFP64', 'IsVec128'))
145 Reg( 'd0', 0, IsScratch=1, CCArg=1, IsFP64=1, Aliases= 'd0, q0, s0, s1'),
146 Reg( 'd1', 1, IsScratch=1, CCArg=2, IsFP64=1, Aliases= 'd1, q0, s2, s3'),
147 Reg( 'd2', 2, IsScratch=1, CCArg=3, IsFP64=1, Aliases= 'd2, q1, s4, s5'),
148 Reg( 'd3', 3, IsScratch=1, CCArg=4, IsFP64=1, Aliases= 'd3, q1, s6, s7'),
149 Reg( 'd4', 4, IsScratch=1, CCArg=5, IsFP64=1, Aliases= 'd4, q2, s8, s9')
[all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceRegistersARM32.h | 31 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
45 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
56 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
67 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
78 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
97 unsigned IsFP64 : 1;
118 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
133 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
168 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
182 return RegTable[RegNum].IsFP64;
[all...] |
| IceTargetLoweringARM32.cpp | 111 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
114 isInt, isI64Pair, isFP32, isFP64, isVec128, \
249 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
258 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
267 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
276 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
285 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
327 Float64Registers[i] = Entry.IsFP64;
348 } else if (Entry.IsFP64) {
[all...] |
