| /external/swiftshader/third_party/subzero/pydir/ |
| gen_arm32_reg_tables.py | 20 IsFP32=0, IsFP64=0, IsVec128=0, Aliases=None):
25 assert not (IsFP32 and IsVec128)
26 assert not (IsFP64 and IsVec128)
27 assert not ((IsGPR) and (IsFP32 or IsFP64 or IsVec128))
54 'IsFP32', 'IsFP64', 'IsVec128'))
180 Reg( 'q0', 0, IsScratch=1, CCArg=1, IsVec128=1, Aliases= 'q0, d0, d1, s0, s1, s2, s3'),
181 Reg( 'q1', 1, IsScratch=1, CCArg=2, IsVec128=1, Aliases= 'q1, d2, d3, s4, s5, s6, s7'),
182 Reg( 'q2', 2, IsScratch=1, CCArg=3, IsVec128=1, Aliases= 'q2, d4, d5, s8, s9, s10, s11'),
183 Reg( 'q3', 3, IsScratch=1, CCArg=4, IsVec128=1, Aliases= 'q3, d6, d7, s12, s13, s14, s15'),
184 Reg( 'q4', 4, IsPreserved=1, IsVec128=1, Aliases= 'q4, d8, d9, s16, s17, s18, s19')
[all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceRegistersARM32.h | 31 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
45 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
56 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
67 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
78 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
98 unsigned IsVec128 : 1;
118 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
133 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
168 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
188 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
[all...] |
| IceTargetLoweringARM32.cpp | 111 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
114 isInt, isI64Pair, isFP32, isFP64, isVec128, \
249 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
258 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
267 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
276 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
285 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
328 VectorRegisters[i] = Entry.IsVec128;
332 QtoSRegisters[i] = Entry.IsVec128 && Entry.Encoding < EncodedReg_q8;
350 } else if (Entry.IsVec128) {
[all...] |
| IceInstARM32.cpp | [all...] |
