| /external/vixl/test/aarch32/ |
| test-disasm-a32.cc | [all...] |
| test-assembler-aarch32.cc | 1182 // This load has a wider range than the Ldrd used below for the same
1187 // With the old pool manager, this Ldrd used to force pool emission before
1190 __ Ldrd(r2, r3, &l1);
1218 // This load has a wider range than the Ldrd used below for the same
1224 // Ldrd below should not need to rewind.
1230 __ Ldrd(r2, r3, &l1);
1277 // Ldrd below (if the pool is not already emitted due to the Ldr).
1283 // This load has a wider range than the Ldrd used below for the same
1288 // Generate nops, in order to bring the checkpoints of the Ldr and Ldrd
1300 __ Ldrd(eq, r2, r3, &l1)
[all...] |
| /external/vixl/test/ |
| test-code-generation-scopes.cc | 354 __ Ldrd(aarch32::r0, aarch32::r1, 0x1234567890abcdef);
430 __ Ldrd(aarch32::r0, aarch32::r1, 0x1234567890abcdef);
709 __ Ldrd(aarch32::r0, aarch32::r1, 0x1234567890abcdef);
717 // otherwise the `Ldrd` will run out of range when we generate the `nop`
|
| /art/compiler/utils/arm/ |
| assembler_arm_vixl.cc | 324 // TODO: Implement indexed load (not available for LDRD) and use it here to avoid the ADD.
351 ___ Ldrd(dest, vixl32::Register(dest.GetCode() + 1), MemOperand(base, offset));
|
| /art/compiler/optimizing/ |
| intrinsics_arm_vixl.cc | [all...] |
| /external/vixl/src/aarch32/ |
| macro-assembler-aarch32.h | 617 void Ldrd(Condition cond, Register rt, Register rt2, RawLiteral* literal) {
634 ldrd(cond, rt, rt2, literal);
637 void Ldrd(Register rt, Register rt2, RawLiteral* literal) {
638 Ldrd(al, rt, rt2, literal);
776 // Generic Ldrd(rt, rt2, data)
777 void Ldrd(Condition cond, Register rt, Register rt2, uint64_t v) {
784 Ldrd(cond, rt, rt2, literal);
787 void Ldrd(Register rt, Register rt2, T v) {
788 Ldrd(al, rt, rt2, v);
[all...] |
| /external/v8/src/arm/ |
| macro-assembler-arm.h | 494 void Ldrd(Register dst1,
[all...] |
| macro-assembler-arm.cc | 885 void MacroAssembler::Ldrd(Register dst1, Register dst2,
894 // Generate two ldr instructions if ldrd is not applicable.
896 ldrd(dst1, dst2, src, cond);
[all...] |
| /external/v8/src/full-codegen/arm/ |
| full-codegen-arm.cc | [all...] |
