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    Searched refs:MMCHS_SYSCTL (Results 1 - 3 of 3) sorted by null

  /device/linaro/bootloader/edk2/Omap35xxPkg/MmcHostDxe/
MmcHostDxe.c 222 // Calculate Clock divider value to program in MMCHS_SYSCTL[CLKD] field.
236 MmioAnd32 (MMCHS_SYSCTL, ~CEN);
239 MmioAndThenOr32 (MMCHS_SYSCTL, ~CLKD_MASK, NewCLKD << 6);
242 while ((MmioRead32 (MMCHS_SYSCTL) & ICS_MASK) != ICS);
245 MmioOr32 (MMCHS_SYSCTL, CEN);
357 MmioAndThenOr32 (MMCHS_SYSCTL, ~DTO_MASK, DTO_VAL);
382 MmioOr32 (MMCHS_SYSCTL, SRC);
383 while ((MmioRead32 (MMCHS_SYSCTL) & SRC));
435 MmioWrite32 (MMCHS_SYSCTL, SRA);
437 while ((MmioRead32 (MMCHS_SYSCTL) & SRA) != 0x0);
    [all...]
  /device/linaro/bootloader/edk2/Omap35xxPkg/MMCHSDxe/
MMCHS.c 100 MmioAnd32 (MMCHS_SYSCTL, ~CEN);
103 MmioAndThenOr32 (MMCHS_SYSCTL, ~CLKD_MASK, NewCLKD << 6);
106 while ((MmioRead32 (MMCHS_SYSCTL) & ICS_MASK) != ICS);
109 MmioOr32 (MMCHS_SYSCTL, CEN);
130 MmioAndThenOr32 (MMCHS_SYSCTL, ~DTO_MASK, DTO_VAL);
154 MmioOr32 (MMCHS_SYSCTL, SRC);
155 while ((MmioRead32 (MMCHS_SYSCTL) & SRC));
322 //Calculate Clock divider value to program in MMCHS_SYSCTL[CLKD] field.
442 MmioOr32 (MMCHS_SYSCTL, SRC);
444 while ((MmioRead32 (MMCHS_SYSCTL) & SRC));
    [all...]
  /device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/
Omap3530MMCHS.h 96 #define MMCHS_SYSCTL (MMCHS1BASE + 0x12C)

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