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    Searched refs:OUT_PKT4 (Results 1 - 6 of 6) sorted by null

  /external/mesa3d/src/gallium/drivers/freedreno/a5xx/
fd5_emit.c 271 OUT_PKT4(ring, REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
374 OUT_PKT4(ring, REG_A5XX_VFD_FETCH(j), 4);
379 OUT_PKT4(ring, REG_A5XX_VFD_DECODE(j), 2);
387 OUT_PKT4(ring, REG_A5XX_VFD_DEST_CNTL(j), 1);
395 OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_0, 1);
418 OUT_PKT4(ring, REG_A5XX_RB_RENDER_COMPONENTS, 1);
437 OUT_PKT4(ring, REG_A5XX_RB_ALPHA_CONTROL, 1);
440 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_CONTROL, 1);
448 OUT_PKT4(ring, REG_A5XX_RB_STENCILREFMASK, 1);
457 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_CNTL, 1)
    [all...]
fd5_gmem.c 95 OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(i), 5);
111 OUT_PKT4(ring, REG_A5XX_SP_FS_MRT_REG(i), 1);
118 OUT_PKT4(ring, REG_A5XX_RB_MRT_FLAG_BUFFER(i), 4);
146 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_BUFFER_INFO, 5);
157 OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
160 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
175 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_INFO, 5);
186 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_INFO, 1);
190 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_BUFFER_INFO, 5);
197 OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO, 1)
    [all...]
fd5_program.c 377 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONTROL_REG, 5);
394 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONFIG, 1);
397 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CNTL, 5);
404 OUT_PKT4(ring, REG_A5XX_SP_VS_CONTROL_REG, 5);
421 OUT_PKT4(ring, REG_A5XX_SP_CS_CONFIG, 1);
424 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONSTLEN, 2);
428 OUT_PKT4(ring, REG_A5XX_HLSQ_FS_CONSTLEN, 2);
432 OUT_PKT4(ring, REG_A5XX_HLSQ_HS_CONSTLEN, 2);
436 OUT_PKT4(ring, REG_A5XX_HLSQ_DS_CONSTLEN, 2);
440 OUT_PKT4(ring, REG_A5XX_HLSQ_GS_CONSTLEN, 2)
    [all...]
fd5_draw.c 55 OUT_PKT4(ring, REG_A5XX_VFD_INDEX_OFFSET, 2);
59 OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1);
250 OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
253 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
257 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_COLOR_DW0, 4);
278 OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
281 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
285 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_COLOR_DW0, 1);
292 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
fd5_emit.h 98 OUT_PKT4(ring, REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO, 5);
150 OUT_PKT4(ring, REG_A5XX_RB_RENDER_CNTL, 1);
  /external/mesa3d/src/gallium/drivers/freedreno/
freedreno_util.h 307 OUT_PKT4(struct fd_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
418 OUT_PKT4(ring, reg, 1);

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