| /art/compiler/utils/arm/ |
| assembler_arm_vixl.h | 89 WITH_FLAGS_DONT_CARE_RD_RN_OP(Orr);
|
| /external/vixl/test/aarch32/ |
| test-disasm-a32.cc | 422 "orr r0, r1, r0\n");
429 COMPARE_BOTH(Orn(r0, r1, 0x00ffffff), "orr r0, r1, #0xff000000\n");
430 COMPARE_BOTH(Orn(r0, r1, 0xff00ffff), "orr r0, r1, #0xff0000\n");
449 "orr r0, r1, r0\n");
453 "orr r0, ip\n");
457 "orr r0, r1, r0\n");
461 "orr r0, ip\n");
469 "orr r0, r1, r0\n");
480 "orr r0, r1, r0\n");
494 "orr r0, ip\n")
[all...] |
| test-simulator-cond-rd-operand-const-a32.cc | 522 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit);
|
| test-simulator-cond-rd-operand-const-t32.cc | 637 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit);
[all...] |
| test-simulator-cond-rd-operand-imm16-t32.cc | 475 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit);
|
| test-simulator-cond-rd-rn-rm-ge-a32.cc | 476 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit);
488 __ Orr(q_bit, q_bit, saved_nzcv_bits);
|
| test-simulator-cond-rd-rn-rm-ge-t32.cc | 476 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit);
488 __ Orr(q_bit, q_bit, saved_nzcv_bits);
|
| test-simulator-cond-rd-rn-rm-q-a32.cc | 460 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit);
472 __ Orr(q_bit, q_bit, saved_nzcv_bits);
|
| test-simulator-cond-rd-rn-rm-q-t32.cc | 460 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit);
472 __ Orr(q_bit, q_bit, saved_nzcv_bits);
|
| test-simulator-cond-rd-rn-rm-sel-a32.cc | 453 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit);
465 __ Orr(q_bit, q_bit, saved_nzcv_bits);
|
| test-simulator-cond-rd-rn-rm-sel-t32.cc | 453 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit);
465 __ Orr(q_bit, q_bit, saved_nzcv_bits);
|
| test-simulator-cond-rd-rn-operand-rm-a32.cc | 126 M(Orr) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-t32.cc | 128 M(Orr) \
[all...] |
| test-simulator-cond-rd-operand-rn-a32.cc | 559 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit);
|
| test-simulator-cond-rd-operand-rn-ror-amount-a32.cc | 624 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit);
[all...] |
| test-simulator-cond-rd-operand-rn-ror-amount-t32.cc | 624 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit);
[all...] |
| test-simulator-cond-rd-operand-rn-t32.cc | 559 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit);
|
| /external/v8/src/arm64/ |
| macro-assembler-arm64-inl.h | 89 void MacroAssembler::Orr(const Register& rd,
94 LogicalMacro(rd, rn, operand, ORR);
[all...] |
| code-stubs-arm64.cc | 121 __ Orr(mantissa, mantissa, 1UL << HeapNumber::kMantissaBits);
283 __ Orr(scratch, left_type, right_type);
[all...] |
| /external/v8/src/regexp/arm64/ |
| regexp-macro-assembler-arm64.cc | 342 __ Orr(w10, w10, 0x20); // Convert capture character to lower-case.
343 __ Orr(w11, w11, 0x20); // Also convert input character.
811 __ Orr(twice_non_position_value(), string_start_minus_one().X(),
[all...] |
| /art/compiler/optimizing/ |
| code_generator_arm_vixl.cc | [all...] |
| /external/vixl/test/aarch64/ |
| test-assembler-aarch64.cc | 321 __ Orr(w10, w0, 0xffffff1);
335 __ Orr(sp, x0, 0x1f7de);
386 __ Orr(sp, xzr, 0x1fff);
390 __ Orr(wsp, wzr, 0xfffffff8);
394 __ Orr(sp, xzr, 0xfffffff8);
696 TEST(orr) {
703 __ Orr(x2, x0, Operand(x1));
704 __ Orr(w3, w0, Operand(w1, LSL, 28));
705 __ Orr(x4, x0, Operand(x1, LSL, 32));
706 __ Orr(x5, x0, Operand(x1, LSR, 4))
[all...] |
| test-disasm-aarch64.cc | 180 COMPARE(dci(0x2a000020), "orr w0, w1, w0");
791 COMPARE(orr(w7, w8, Operand(0xaaaaaaaa)), "orr w7, w8, #0xaaaaaaaa");
792 COMPARE(orr(x9, x10, Operand(0x5555555555555555)),
793 "orr x9, x10, #0x5555555555555555")
[all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceInstARM32.h | 408 Orr,
[all...] |
| /external/v8/src/compiler/arm64/ |
| code-generator-arm64.cc | [all...] |
