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Searched
refs:PL1
(Results
1 - 4
of
4
) sorted by null
/device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/Arm/
ArmV7ArchTimerSupport.S
31
mrc p15, 0, r0, c14, c1, 0 @ Read CNTK_CTL (Timer
PL1
Control Register)
35
mcr p15, 0, r0, c14, c1, 0 @ Write to CNTK_CTL (Timer
PL1
Control Register)
39
mrc p15, 0, r0, c14, c2, 0 @ Read CNTP_TVAL (
PL1
physical timer value register)
43
mcr p15, 0, r0, c14, c2, 0 @ Write to CNTP_TVAL (
PL1
physical timer value register)
47
mrc p15, 0, r0, c14, c2, 1 @ Read CNTP_CTL (
PL1
Physical Timer Control Register)
51
mcr p15, 0, r0, c14, c2, 1 @ Write to CNTP_CTL (
PL1
Physical Timer Control Register)
/external/python/cpython2/Lib/plat-unixware7/
IN.py
404
PL1
= 1
413
PLTIMEOUT =
PL1
418
PLMIN =
PL1
/external/elfutils/libdw/
known-dwarf.h
329
DWARF_ONE_KNOWN_DW_LANG (
PL1
, DW_LANG_PL1) \
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all
...]
/external/abi-compliance-checker/
abi-compliance-checker.pl
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...]
Completed in 156 milliseconds