| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/MultiPlatformLib/ |
| MultiPlatformLib.c | 71 PlatformInfoHob->PciData.PciExpressSize = PcieLength;
72 PlatformInfoHob->PciData.PciExpressBase = PcdGet64 (PcdPciExpressBaseAddress);
74 PlatformInfoHob->PciData.PciResourceMem32Base = (UINT32) (PlatformInfoHob->PciData.PciExpressBase - RES_MEM32_MIN_LEN);
75 PlatformInfoHob->PciData.PciResourceMem32Limit = (UINT32) (PlatformInfoHob->PciData.PciExpressBase -1);
77 PlatformInfoHob->PciData.PciResourceMem64Base = RES_MEM64_36_BASE;
78 PlatformInfoHob->PciData.PciResourceMem64Limit = RES_MEM64_36_LIMIT;
81 PlatformInfoHob->MemData.MemMir0 = PlatformInfoHob->PciData.PciResourceMem64Base;
82 PlatformInfoHob->MemData.MemMir1 = PlatformInfoHob->PciData.PciResourceMem64Limit + 1;
[all...] |
| /device/linaro/bootloader/edk2/DuetPkg/PciBusNoEnumerationDxe/ |
| PciDeviceSupport.c | 477 PCI_TYPE01 PciData;
490 sizeof (PciData),
491 &PciData
494 if ((((PciData.Bridge.IoBase & 0xF) == 0) &&
495 (PciData.Bridge.IoBase != 0 || PciData.Bridge.IoLimit != 0)) ||
496 (((PciData.Bridge.IoBase & 0xF) == 1) &&
497 ((PciData.Bridge.IoBase & 0xF0) != 0 || (PciData.Bridge.IoLimit & 0xF0) != 0 || PciData.Bridge.IoBaseUpper16 != 0 || PciData.Bridge.IoLimitUpper16 != 0))) {
[all...] |
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformInitPei/ |
| MemoryCallback.c | 88 DEBUG ((EFI_D_ERROR, "PCIE OSBASE: %lX\n", PlatformInfo->PciData.PciExpressBase));
92 PlatformInfo->PciData.PciExpressBase,
93 PlatformInfo->PciData.PciExpressSize)
98 PlatformInfo->PciData.PciResourceMem32Base,
99 PlatformInfo->PciData.PciResourceMem32Limit)
104 PlatformInfo->PciData.PciResourceMem64Base,
105 PlatformInfo->PciData.PciResourceMem64Limit)
116 HecBaseHigh = (UINT32) RShiftU64 (PlatformInfo->PciData.PciExpressBase, 28);
280 PlatformInfo->PciData.PciExpressBase,
281 PlatformInfo->PciData.PciExpressSize
[all...] |
| PlatformInfoInit.c | 162 PlatformInfoHob->PciData.PciResourceMem32Base = MemoryCeiling;
|
| /device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/ |
| LegacyIde.c | 273 PCI_TYPE00 PciData;
290 Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0, sizeof (PciData), &PciData);
298 if ((PciData.Hdr.ClassCode[2] != PCI_CLASS_MASS_STORAGE) ||
299 (PciData.Hdr.ClassCode[1] != PCI_CLASS_MASS_STORAGE_IDE)) {
307 if ((PciData.Hdr.ClassCode[0] & IDE_PI_REGISTER_PNE) == 0) {
311 if ((PciData.Hdr.ClassCode[0] & IDE_PI_REGISTER_SNE) == 0) {
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/SataControllerDxe/ |
| SataController.c | 300 PCI_TYPE00 PciData;
325 sizeof (PciData.Hdr.ClassCode),
326 PciData.Hdr.ClassCode
332 if (IS_PCI_IDE (&PciData) || IS_PCI_SATADPA (&PciData)) {
363 PCI_TYPE00 PciData;
414 sizeof (PciData.Hdr.ClassCode),
415 PciData.Hdr.ClassCode
419 if (IS_PCI_IDE (&PciData)) {
422 } else if (IS_PCI_SATADPA (&PciData)) {
[all...] |
| /device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/ |
| Ide.c | 286 PCI_TYPE00 PciData;
292 sizeof (PciData),
293 &PciData
300 if ((PciData.Hdr.ClassCode[0] & IDE_PRIMARY_OPERATING_MODE) == 0) {
304 (UINT16)((PciData.Device.Bar[4] & 0x0000fff0));
309 if ((PciData.Device.Bar[0] & BIT0) == 0 ||
310 (PciData.Device.Bar[1] & BIT0) == 0) {
315 (UINT16) (PciData.Device.Bar[0] & 0x0000fff8);
317 (UINT16) ((PciData.Device.Bar[1] & 0x0000fffc) + 2);
319 (UINT16) ((PciData.Device.Bar[4] & 0x0000fff0));
[all...] |
| IdeBus.c | 152 PCI_TYPE00 PciData;
253 sizeof (PciData),
254 &PciData
261 if ((PciData.Hdr.ClassCode[2] != PCI_CLASS_MASS_STORAGE) || (PciData.Hdr.ClassCode[1] != PCI_SUB_CLASS_IDE)) {
[all...] |
| /device/linaro/bootloader/edk2/CorebootModulePkg/SataControllerDxe/ |
| SataController.c | 330 PCI_TYPE00 PciData;
355 sizeof (PciData.Hdr.ClassCode),
356 PciData.Hdr.ClassCode
362 if (IS_PCI_IDE (&PciData) || IS_PCI_SATADPA (&PciData)) {
393 PCI_TYPE00 PciData;
444 sizeof (PciData.Hdr.ClassCode),
445 PciData.Hdr.ClassCode
449 if (IS_PCI_IDE (&PciData)) {
452 } else if (IS_PCI_SATADPA (&PciData)) {
[all...] |
| /device/linaro/bootloader/edk2/DuetPkg/SataControllerDxe/ |
| SataController.c | 330 PCI_TYPE00 PciData;
355 sizeof (PciData.Hdr.ClassCode),
356 PciData.Hdr.ClassCode
362 if (IS_PCI_IDE (&PciData) || IS_PCI_SATADPA (&PciData)) {
393 PCI_TYPE00 PciData;
444 sizeof (PciData.Hdr.ClassCode),
445 PciData.Hdr.ClassCode
449 if (IS_PCI_IDE (&PciData)) {
452 } else if (IS_PCI_SATADPA (&PciData)) {
[all...] |
| /device/linaro/bootloader/edk2/OvmfPkg/SataControllerDxe/ |
| SataController.c | 330 PCI_TYPE00 PciData;
355 sizeof (PciData.Hdr.ClassCode),
356 PciData.Hdr.ClassCode
362 if (IS_PCI_IDE (&PciData) || IS_PCI_SATADPA (&PciData)) {
394 PCI_TYPE00 PciData;
460 sizeof (PciData.Hdr.ClassCode),
461 PciData.Hdr.ClassCode
467 if (IS_PCI_IDE (&PciData)) {
470 } else if (IS_PCI_SATADPA (&PciData)) {
[all...] |
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/UfsPciHcDxe/ |
| UfsPciHcDxe.c | 423 PCI_TYPE00 PciData;
479 sizeof (PciData),
480 &PciData
492 // Since we already got the PciData, we can close protocol to avoid to carry it on for multiple exit points.
504 if (PciData.Hdr.ClassCode[2] == PCI_CLASS_MASS_STORAGE) {
505 if (PciData.Hdr.ClassCode[1] == 0x09 ) { //UFS Controller Subclass
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/ |
| IdeMode.c | 934 PCI_TYPE00 PciData;
947 sizeof (PciData),
948 &PciData
955 BusMasterBaseAddr = (UINT16) ((PciData.Device.Bar[4] & 0x0000fff0));
957 if ((PciData.Hdr.ClassCode[0] & IDE_PRIMARY_OPERATING_MODE) == 0) {
964 if ((PciData.Device.Bar[0] & BIT0) == 0 ||
965 (PciData.Device.Bar[1] & BIT0) == 0) {
969 CommandBlockBaseAddr = (UINT16) (PciData.Device.Bar[0] & 0x0000fff8);
970 ControlBlockBaseAddr = (UINT16) ((PciData.Device.Bar[1] & 0x0000fffc) + 2);
987 if ((PciData.Hdr.ClassCode[0] & IDE_SECONDARY_OPERATING_MODE) == 0) {
[all...] |
| AtaAtapiPassThru.c | 533 PCI_TYPE00 PciData;
612 sizeof (PciData.Hdr.ClassCode),
613 PciData.Hdr.ClassCode
619 if (IS_PCI_IDE (&PciData) || IS_PCI_SATADPA (&PciData)) {
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Drivers/Block/DwUfsHcDxe/ |
| DwUfsHcDxe.c | 637 PCI_TYPE00 PciData;
692 sizeof (PciData),
693 &PciData
706 // Since we already got the PciData, we can close protocol to avoid to carry it on for multiple exit points.
718 if (PciData.Hdr.ClassCode[2] == PCI_CLASS_MASS_STORAGE) {
719 if (PciData.Hdr.ClassCode[1] == 0x09 ) { //UFS Controller Subclass
[all...] |
| /device/linaro/bootloader/edk2/DuetPkg/PciRootBridgeNoEnumerationDxe/Ia32/ |
| PcatIo.c | 98 UINTN PciData;
170 PciData = (UINTN)PrivateData->PciData + PciDataStride;
174 This->Io.Write (This, Width, PciData, 1, UserBuffer);
176 This->Io.Read (This, Width, PciData, 1, UserBuffer);
|
| /device/linaro/bootloader/edk2/DuetPkg/PciRootBridgeNoEnumerationDxe/X64/ |
| PcatIo.c | 98 UINTN PciData;
170 PciData = (UINTN)PrivateData->PciData + PciDataStride;
174 This->Io.Write (This, Width, PciData, 1, UserBuffer);
176 This->Io.Read (This, Width, PciData, 1, UserBuffer);
|
| /device/linaro/bootloader/edk2/OptionRomPkg/AtapiPassThruDxe/ |
| AtapiPassThru.c | [all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Drivers/SdMmc/DwMmcHcDxe/ |
| DwMmcHcDxe.c | 435 PCI_TYPE00 PciData;
501 sizeof (PciData),
502 &PciData
514 // Since we already got the PciData, we can close protocol to avoid to carry it
527 if ((PciData.Hdr.ClassCode[2] == PCI_CLASS_SYSTEM_PERIPHERAL) &&
528 (PciData.Hdr.ClassCode[1] == PCI_SUBCLASS_SD_HOST_CONTROLLER) &&
529 ((PciData.Hdr.ClassCode[0] == 0x00) || (PciData.Hdr.ClassCode[0] == 0x01))) {
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Drivers/SdMmc/XenonDxe/ |
| SdMmcPciHcDxe.c | 386 PCI_TYPE00 PciData;
443 sizeof (PciData),
444 &PciData
456 // Since we already got the PciData, we can close protocol to avoid to carry it
469 if ((PciData.Hdr.ClassCode[2] == PCI_CLASS_SYSTEM_PERIPHERAL) &&
470 (PciData.Hdr.ClassCode[1] == PCI_SUBCLASS_SD_HOST_CONTROLLER) &&
471 ((PciData.Hdr.ClassCode[0] == 0x00) || (PciData.Hdr.ClassCode[0] == 0x01))) {
[all...] |
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/ |
| SdMmcPciHcDxe.c | 383 PCI_TYPE00 PciData;
440 sizeof (PciData),
441 &PciData
453 // Since we already got the PciData, we can close protocol to avoid to carry it
466 if ((PciData.Hdr.ClassCode[2] == PCI_CLASS_SYSTEM_PERIPHERAL) &&
467 (PciData.Hdr.ClassCode[1] == PCI_SUBCLASS_SD_HOST_CONTROLLER) &&
468 ((PciData.Hdr.ClassCode[0] == 0x00) || (PciData.Hdr.ClassCode[0] == 0x01))) {
[all...] |
| /device/linaro/bootloader/edk2/DuetPkg/PciRootBridgeNoEnumerationDxe/ |
| PcatPciRootBridge.h | 70 UINT64 PciData;
|
| /device/linaro/bootloader/edk2/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/ |
| PciRootBridgeIo.c | 85 PrivateData->PciData = 0xCFC;
783 UINTN PciData;
817 PciData = PrivateData->PciData + PciDataStride;
822 This->Io.Write (This, Width, PciData, 1, UserBuffer);
824 This->Io.Read (This, Width, PciData, 1, UserBuffer);
[all...] |
| PciRootBridge.h | 86 UINTN PciData;
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/ |
| PciHostBridge.h | 476 UINTN PciData;
|
