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    Searched refs:PcieStat (Results 1 - 2 of 2) sorted by null

  /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/
PcieInitLib.c 641 U_SC_PCIE0_SYS_STATE4 PcieStat;
646 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
647 val = PcieStat.UInt32;
667 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
668 val = PcieStat.UInt32;
695 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
696 val = PcieStat.UInt32;
716 U_SC_PCIE0_SYS_STATE4 PcieStat;
720 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
721 val = PcieStat.UInt32;
    [all...]
  /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/
PcieInitLib.c 813 U_SC_PCIE0_SYS_STATE4 PcieStat;
816 RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x131c, PcieStat.UInt32);
817 Value = PcieStat.UInt32;
824 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
825 Value = PcieStat.UInt32;
    [all...]

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