| /system/core/libpixelflinger/codeflinger/ |
| ARMAssemblerInterface.h | 124 int Rd, int Rn,
129 int Rd, int Rm, int Rs, int Rn) = 0;
131 int Rd, int Rm, int Rs) = 0;
154 virtual void LDR (int cc, int Rd,
156 virtual void LDRB(int cc, int Rd,
158 virtual void STR (int cc, int Rd,
160 virtual void STRB(int cc, int Rd,
163 virtual void LDRH (int cc, int Rd,
165 virtual void LDRSB(int cc, int Rd,
167 virtual void LDRSH(int cc, int Rd,
[all...] |
| ARMAssemblerInterface.cpp | 69 void ARMAssemblerInterface::ADDR_LDR(int cc, int Rd,
72 LDR(cc, Rd, Rn, offset);
74 void ARMAssemblerInterface::ADDR_STR(int cc, int Rd,
77 STR(cc, Rd, Rn, offset);
80 int Rd, int Rn, uint32_t Op2)
82 dataProcessing(opADD, cc, s, Rd, Rn, Op2);
85 int Rd, int Rn, uint32_t Op2)
87 dataProcessing(opSUB, cc, s, Rd, Rn, Op2);
|
| ARMAssemblerProxy.cpp | 161 int Rd, int Rn, uint32_t Op2)
163 mTarget->dataProcessing(opcode, cc, s, Rd, Rn, Op2);
166 void ARMAssemblerProxy::MLA(int cc, int s, int Rd, int Rm, int Rs, int Rn) {
167 mTarget->MLA(cc, s, Rd, Rm, Rs, Rn);
169 void ARMAssemblerProxy::MUL(int cc, int s, int Rd, int Rm, int Rs) {
170 mTarget->MUL(cc, s, Rd, Rm, Rs);
212 void ARMAssemblerProxy::LDR(int cc, int Rd, int Rn, uint32_t offset) {
213 mTarget->LDR(cc, Rd, Rn, offset);
215 void ARMAssemblerProxy::LDRB(int cc, int Rd, int Rn, uint32_t offset) {
216 mTarget->LDRB(cc, Rd, Rn, offset)
[all...] |
| Arm64Assembler.cpp | 340 int s, int Rd, int Rn, uint32_t Op2)
397 case opADD: *mPC++ = A64_ADD_W(Rd, Rn, Rm, shift, amount); break;
398 case opAND: *mPC++ = A64_AND_W(Rd, Rn, Rm, shift, amount); break;
399 case opORR: *mPC++ = A64_ORR_W(Rd, Rn, Rm, shift, amount); break;
400 case opMVN: *mPC++ = A64_ORN_W(Rd, Rn, Rm, shift, amount); break;
401 case opSUB: *mPC++ = A64_SUB_W(Rd, Rn, Rm, shift, amount, s);break;
408 int s, int Rd, int Rn, uint32_t Op2)
415 Wd = Rd;
455 *mPC++ = A64_CSEL_W(Rd, mTmpReg1, Rd, cc)
[all...] |
| Arm64Assembler.h | 99 int Rd, int Rn,
102 int Rd, int Rm, int Rs, int Rn);
104 int Rd, int Rm, int Rs);
123 virtual void ADDR_LDR(int cc, int Rd,
125 virtual void ADDR_ADD(int cc, int s, int Rd,
127 virtual void ADDR_SUB(int cc, int s, int Rd,
129 virtual void ADDR_STR (int cc, int Rd,
132 virtual void LDR (int cc, int Rd,
134 virtual void LDRB(int cc, int Rd,
136 virtual void STR (int cc, int Rd,
[all...] |
| ARMAssemblerProxy.h | 80 int Rd, int Rn,
83 int Rd, int Rm, int Rs, int Rn);
85 int Rd, int Rm, int Rs);
104 virtual void LDR (int cc, int Rd,
106 virtual void LDRB(int cc, int Rd,
108 virtual void STR (int cc, int Rd,
110 virtual void STRB(int cc, int Rd,
112 virtual void LDRH (int cc, int Rd,
114 virtual void LDRSB(int cc, int Rd,
116 virtual void LDRSH(int cc, int Rd,
[all...] |
| ARMAssembler.h | 91 int Rd, int Rn,
94 int Rd, int Rm, int Rs, int Rn);
96 int Rd, int Rm, int Rs);
115 virtual void LDR (int cc, int Rd,
117 virtual void LDRB(int cc, int Rd,
119 virtual void STR (int cc, int Rd,
121 virtual void STRB(int cc, int Rd,
123 virtual void LDRH (int cc, int Rd,
125 virtual void LDRSB(int cc, int Rd,
127 virtual void LDRSH(int cc, int Rd,
[all...] |
| MIPS64Assembler.cpp | 334 void ArmToMips64Assembler::protectConditionalOperands(int Rd)
336 if (Rd == cond.r1) {
340 if (cond.type == CMP_COND && Rd == cond.r2) {
392 int s, int Rd, int Rn, uint32_t Op2)
397 protectConditionalOperands(Rd);
408 mMips->AND(Rd, Rn, src);
410 mMips->ANDI(Rd, Rn, src);
417 mMips->ADDU(Rd, Rn, src);
419 mMips->ADDIU(Rd, Rn, src);
426 mMips->SUBU(Rd, Rn, src)
[all...] |
| MIPSAssembler.cpp | 349 void ArmToMipsAssembler::protectConditionalOperands(int Rd)
351 if (Rd == cond.r1) {
355 if (cond.type == CMP_COND && Rd == cond.r2) {
412 int s, int Rd, int Rn, uint32_t Op2)
418 protectConditionalOperands(Rd);
429 mMips->AND(Rd, Rn, src);
431 mMips->ANDI(Rd, Rn, src);
438 mMips->ADDU(Rd, Rn, src);
440 mMips->ADDIU(Rd, Rn, src);
447 mMips->SUBU(Rd, Rn, src)
[all...] |
| MIPSAssembler.h | 91 int Rd, int Rn,
94 int Rd, int Rm, int Rs, int Rn);
96 int Rd, int Rm, int Rs);
115 virtual void LDR (int cc, int Rd,
117 virtual void LDRB(int cc, int Rd,
119 virtual void STR (int cc, int Rd,
121 virtual void STRB(int cc, int Rd,
123 virtual void LDRH (int cc, int Rd,
125 virtual void LDRSB(int cc, int Rd,
127 virtual void LDRSH(int cc, int Rd,
[all...] |
| ARMAssembler.cpp | 203 int s, int Rd, int Rn, uint32_t Op2)
205 *mPC++ = (cc<<28) | (opcode<<21) | (s<<20) | (Rn<<16) | (Rd<<12) | Op2;
215 int Rd, int Rm, int Rs, int Rn) {
216 if (Rd == Rm) { int t = Rm; Rm=Rs; Rs=t; }
217 LOG_FATAL_IF(Rd==Rm, "MLA(r%u,r%u,r%u,r%u)", Rd,Rm,Rs,Rn);
219 (Rd<<16) | (Rn<<12) | (Rs<<8) | 0x90 | Rm;
222 int Rd, int Rm, int Rs) {
223 if (Rd == Rm) { int t = Rm; Rm=Rs; Rs=t; }
224 LOG_FATAL_IF(Rd==Rm, "MUL(r%u,r%u,r%u)", Rd,Rm,Rs)
[all...] |
| MIPS64Assembler.h | 96 int Rd, int Rn,
99 int Rd, int Rm, int Rs, int Rn);
101 int Rd, int Rm, int Rs);
120 virtual void LDR (int cc, int Rd,
122 virtual void LDRB(int cc, int Rd,
124 virtual void STR (int cc, int Rd,
126 virtual void STRB(int cc, int Rd,
128 virtual void LDRH (int cc, int Rd,
130 virtual void LDRSB(int cc, int Rd,
132 virtual void LDRSH(int cc, int Rd,
[all...] |
| /prebuilts/go/darwin-x86/src/crypto/sha1/ |
| sha1block_arm.s | 31 #define Rd R5 // SHA-1 accumulator
83 #define FUNC1(Ra, Rb, Rc, Rd, Re) \
86 AND Rd, Rt1, Rt1 ; \
90 #define FUNC2(Ra, Rb, Rc, Rd, Re) \
92 EOR Rd, Rt1, Rt1
96 #define FUNC3(Ra, Rb, Rc, Rd, Re) \
99 AND Rd, Rt0, Rt0 ; \
107 #define MIX(Ra, Rb, Rc, Rd, Re) \
113 #define ROUND1(Ra, Rb, Rc, Rd, Re) \
115 FUNC1(Ra, Rb, Rc, Rd, Re) ;
[all...] |
| /prebuilts/go/linux-x86/src/crypto/sha1/ |
| sha1block_arm.s | 31 #define Rd R5 // SHA-1 accumulator
83 #define FUNC1(Ra, Rb, Rc, Rd, Re) \
86 AND Rd, Rt1, Rt1 ; \
90 #define FUNC2(Ra, Rb, Rc, Rd, Re) \
92 EOR Rd, Rt1, Rt1
96 #define FUNC3(Ra, Rb, Rc, Rd, Re) \
99 AND Rd, Rt0, Rt0 ; \
107 #define MIX(Ra, Rb, Rc, Rd, Re) \
113 #define ROUND1(Ra, Rb, Rc, Rd, Re) \
115 FUNC1(Ra, Rb, Rc, Rd, Re) ;
[all...] |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| mul-overlap.l | 2 [^:]*:5: Rd and Rm should be different in mul
3 [^:]*:6: Rd and Rm should be different in mla
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64PBQPRegAlloc.h | 29 // parity(Rd) == parity(Ra).
31 bool addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
34 void addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
|
| AArch64PBQPRegAlloc.cpp | 159 bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd,
161 if (Rd == Ra)
166 if (TRI->isPhysicalRegister(Rd) || TRI->isPhysicalRegister(Ra)) {
167 DEBUG(dbgs() << "Rd is a physical reg:" << TRI->isPhysicalRegister(Rd)
174 PBQPRAGraph::NodeId node1 = G.getMetadata().getNodeIdForVReg(Rd);
187 const LiveInterval &ld = LIs.getInterval(Rd);
243 void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd,
249 if (Rd != Ra) {
251 << PrintReg(Rd, TRI) << '\n';)
[all...] |
| /prebuilts/go/darwin-x86/src/crypto/md5/ |
| md5block_arm.s | 15 #define Rd R5 // MD5 accumulator
65 MOVM.IA (Rc0), [Ra,Rb,Rc,Rd]
69 #define ROUND1(Ra, Rb, Rc, Rd, index, shift, Rconst) \
70 EOR Rc, Rd, Rt0 ; \
72 EOR Rd, Rt0 ; \
80 ROUND1(Ra, Rb, Rc, Rd, 0, 7, Rc0)
81 ROUND1(Rd, Ra, Rb, Rc, 1, 12, Rc1)
82 ROUND1(Rc, Rd, Ra, Rb, 2, 17, Rc2)
83 ROUND1(Rb, Rc, Rd, Ra, 3, 22, Rc3)
86 ROUND1(Ra, Rb, Rc, Rd, 4, 7, Rc0
[all...] |
| /prebuilts/go/linux-x86/src/crypto/md5/ |
| md5block_arm.s | 15 #define Rd R5 // MD5 accumulator
65 MOVM.IA (Rc0), [Ra,Rb,Rc,Rd]
69 #define ROUND1(Ra, Rb, Rc, Rd, index, shift, Rconst) \
70 EOR Rc, Rd, Rt0 ; \
72 EOR Rd, Rt0 ; \
80 ROUND1(Ra, Rb, Rc, Rd, 0, 7, Rc0)
81 ROUND1(Rd, Ra, Rb, Rc, 1, 12, Rc1)
82 ROUND1(Rc, Rd, Ra, Rb, 2, 17, Rc2)
83 ROUND1(Rb, Rc, Rd, Ra, 3, 22, Rc3)
86 ROUND1(Ra, Rb, Rc, Rd, 4, 7, Rc0
[all...] |
| /prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/ |
| decode.go | 948 Rd := x & (1<<5 - 1)
950 return B0 + Reg(Rd)
952 return H0 + Reg(Rd)
954 return S0 + Reg(Rd)
956 return D0 + Reg(Rd)
963 Rd := x & (1<<5 - 1)
965 return B0 + Reg(Rd)
967 return H0 + Reg(Rd)
969 return S0 + Reg(Rd)
976 Rd := x & (1<<5 - 1
[all...] |
| /prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/ |
| decode.go | 948 Rd := x & (1<<5 - 1)
950 return B0 + Reg(Rd)
952 return H0 + Reg(Rd)
954 return S0 + Reg(Rd)
956 return D0 + Reg(Rd)
963 Rd := x & (1<<5 - 1)
965 return B0 + Reg(Rd)
967 return H0 + Reg(Rd)
969 return S0 + Reg(Rd)
976 Rd := x & (1<<5 - 1
[all...] |
| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmDisassemblerLib/ |
| ArmDisassembler.c | 169 UINT32 Rn, Rd, Rm;
183 Rd = (OpCode >> 12) & 0xf;
196 // A4.1.27 LDREX{<cond>} <Rd>, [<Rn>]
197 AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]);
199 // A4.1.103 STREX{<cond>} <Rd>, <Rm>, [<Rn>]
200 AsciiSPrint (Buf, Size, "STREX%a %a, %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn], gReg[Rn]);
226 Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", L ? "LDR" : "STR", COND (OpCode), BYTE (B), (!(P) && W) ? "T":"", gReg[Rd]);
297 // LDR|STR{<cond>}H|SH|SB|D <Rd>, <addressing_mode>
316 Index = AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]);
346 // A4.1.108 SWP SWP{<cond>}B <Rd>, <Rm>, [<Rn>]
[all...] |
| /system/core/libpixelflinger/tests/arch-mips64/assembler/ |
| mips64_assembler_test.cpp | 371 void dataOpTest(dataOpTest_t test, ArmToMips64Assembler *a64asm, uint32_t Rd = R_v1,
385 regs[Rd] = test.RdValue;
411 case INSTR_ADD: a64asm->ADD(test.cond, test.setFlags, Rd,Rn,op2); break;
412 case INSTR_SUB: a64asm->SUB(test.cond, test.setFlags, Rd,Rn,op2); break;
413 case INSTR_RSB: a64asm->RSB(test.cond, test.setFlags, Rd,Rn,op2); break;
414 case INSTR_AND: a64asm->AND(test.cond, test.setFlags, Rd,Rn,op2); break;
415 case INSTR_ORR: a64asm->ORR(test.cond, test.setFlags, Rd,Rn,op2); break;
416 case INSTR_BIC: a64asm->BIC(test.cond, test.setFlags, Rd,Rn,op2); break;
417 case INSTR_MUL: a64asm->MUL(test.cond, test.setFlags, Rd,Rm,Rs); break;
418 case INSTR_MLA: a64asm->MLA(test.cond, test.setFlags, Rd,Rm,Rs,Rn); break
[all...] |
| /prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/arm/armasm/ |
| tables.go | [all...] |
| /prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/arm/armasm/ |
| tables.go | [all...] |
