HomeSort by relevance Sort by last modified time
    Searched refs:Reg (Results 1 - 25 of 1492) sorted by null

1 2 3 4 5 6 7 8 91011>>

  /art/compiler/debug/dwarf/
register.h 24 class Reg {
26 explicit Reg(int reg_num) : num_(reg_num) { }
38 static Reg ArmCore(int num) { return Reg(num); } // R0-R15.
39 static Reg ArmFp(int num) { return Reg(64 + num); } // S0?S31.
40 static Reg ArmDp(int num) { return Reg(256 + num); } // D0?D31.
41 static Reg Arm64Core(int num) { return Reg(num); } // X0-X31
    [all...]
  /device/linaro/bootloader/edk2/ArmPkg/Include/
AsmMacroIoLib.h 31 #define MOV32(Reg, Val) \
32 movw Reg, #(Val) & 0xffff ; \
33 movt Reg, #(Val) >> 16
35 #define ADRL(Reg, Sym) \
36 movw Reg, #:lower16:(Sym) - (. + 16) ; \
37 movt Reg, #:upper16:(Sym) - (. + 12) ; \
38 add Reg, Reg, pc
40 #define LDRL(Reg, Sym) \
41 movw Reg, #:lower16:(Sym) - (. + 16) ; \
    [all...]
  /external/swiftshader/third_party/subzero/pydir/
gen_arm32_reg_tables.py 60 class Reg(object):
82 Reg( 'r0', 0, IsScratch=1, CCArg=1, IsGPR = 1, IsInt=1, Aliases= 'r0, r0r1'),
83 Reg( 'r1', 1, IsScratch=1, CCArg=2, IsGPR = 1, IsInt=1, Aliases= 'r1, r0r1'),
84 Reg( 'r2', 2, IsScratch=1, CCArg=3, IsGPR = 1, IsInt=1, Aliases= 'r2, r2r3'),
85 Reg( 'r3', 3, IsScratch=1, CCArg=4, IsGPR = 1, IsInt=1, Aliases= 'r3, r2r3'),
86 Reg( 'r4', 4, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r4, r4r5'),
87 Reg( 'r5', 5, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r5, r4r5'),
88 Reg( 'r6', 6, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r6, r6r7'),
89 Reg( 'r7', 7, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r7, r6r7'),
90 Reg( 'r8', 8, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r8, r8r9')
    [all...]
  /external/clang/lib/StaticAnalyzer/Core/
DynamicTypeMap.cpp 22 const MemRegion *Reg) {
23 Reg = Reg->StripCasts();
26 const DynamicTypeInfo *GDMType = State->get<DynamicTypeMap>(Reg);
31 if (const TypedRegion *TR = dyn_cast<TypedRegion>(Reg))
34 if (const SymbolicRegion *SR = dyn_cast<SymbolicRegion>(Reg)) {
42 ProgramStateRef setDynamicTypeInfo(ProgramStateRef State, const MemRegion *Reg,
44 Reg = Reg->StripCasts();
45 ProgramStateRef NewState = State->set<DynamicTypeMap>(Reg, NewTy)
    [all...]
  /external/llvm/lib/Target/WebAssembly/
WebAssemblyMachineFunctionInfo.cpp 23 unsigned Reg = UnusedReg;
24 WARegs.resize(MF.getRegInfo().getNumVirtRegs(), Reg);
  /external/swiftshader/third_party/LLVM/lib/Target/Sparc/
SparcMachineFunctionInfo.h 37 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; }
43 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
  /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
SystemZMachineFunctionInfo.h 43 void setLowReg(unsigned Reg) { LowReg = Reg; }
46 void setHighReg(unsigned Reg) { HighReg = Reg; }
  /external/llvm/lib/Target/Hexagon/
HexagonRDF.cpp 23 if (TargetRegisterInfo::isVirtualRegister(RA.Reg) &&
24 TargetRegisterInfo::isVirtualRegister(RB.Reg)) {
26 if (RA.Reg == RB.Reg) {
42 if (!TargetRegisterInfo::isPhysicalRegister(RR.Reg)) {
43 assert(TargetRegisterInfo::isVirtualRegister(RR.Reg));
45 bool HasLo = RRs.count({RR.Reg, Hexagon::subreg_loreg});
46 bool HasHi = RRs.count({RR.Reg, Hexagon::subreg_hireg});
53 unsigned Lo = TRI.getSubReg(RR.Reg, Hexagon::subreg_loreg);
54 unsigned Hi = TRI.getSubReg(RR.Reg, Hexagon::subreg_hireg)
    [all...]
  /external/llvm/lib/CodeGen/
MachineRegisterInfo.cpp 39 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
41 VRegInfo[Reg].first = RC;
44 void MachineRegisterInfo::setRegBank(unsigned Reg,
46 VRegInfo[Reg].first = &RegBank;
50 MachineRegisterInfo::constrainRegClass(unsigned Reg,
53 const TargetRegisterClass *OldRC = getRegClass(Reg);
62 setRegClass(Reg, NewRC);
67 MachineRegisterInfo::recomputeRegClass(unsigned Reg) {
69 const TargetRegisterClass *OldRC = getRegClass(Reg);
78 for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
    [all...]
  /external/llvm/lib/Target/X86/
X86MachineFunctionInfo.cpp 25 unsigned Reg = *CSR;
28 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
  /external/swiftshader/third_party/LLVM/lib/CodeGen/
AllocationOrder.h 57 unsigned Reg = *Pos++;
58 if (Reg != Hint)
59 return Reg;
  /external/capstone/arch/SystemZ/
SystemZMCTargetDesc.h 32 unsigned SystemZMC_getFirstReg(unsigned Reg);
  /external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
DynamicTypeMap.h 40 const MemRegion *Reg);
43 ProgramStateRef setDynamicTypeInfo(ProgramStateRef State, const MemRegion *Reg,
48 const MemRegion *Reg, QualType NewTy,
50 return setDynamicTypeInfo(State, Reg,
  /external/llvm/lib/Target/Sparc/
SparcMachineFunctionInfo.h 43 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; }
49 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
  /external/swiftshader/third_party/LLVM/lib/Target/Alpha/
AlphaMachineFunctionInfo.h 48 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; }
51 void setGlobalRetAddr(unsigned Reg) { GlobalRetAddr = Reg; }
  /external/swiftshader/third_party/LLVM/lib/Target/PTX/
PTXMachineFunctionInfo.h 82 void addRetReg(unsigned Reg) {
83 if (!RegRets.count(Reg)) {
84 RegRets.insert(Reg);
88 RegNames[Reg] = name;
93 void addArgReg(unsigned Reg) {
94 RegArgs.insert(Reg);
98 RegNames[Reg] = name;
103 void addVirtualRegister(const TargetRegisterClass *TRC, unsigned Reg) {
107 if (!RegRets.count(Reg) && !RegArgs.count(Reg)) {
    [all...]
  /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
DynamicTypeMap.h 40 const MemRegion *Reg);
43 ProgramStateRef setDynamicTypeInfo(ProgramStateRef State, const MemRegion *Reg,
48 const MemRegion *Reg, QualType NewTy,
50 return setDynamicTypeInfo(State, Reg,
  /prebuilts/clang/host/darwin-x86/clang-4393122/include/clang/StaticAnalyzer/Core/PathSensitive/
DynamicTypeMap.h 40 const MemRegion *Reg);
43 ProgramStateRef setDynamicTypeInfo(ProgramStateRef State, const MemRegion *Reg,
48 const MemRegion *Reg, QualType NewTy,
50 return setDynamicTypeInfo(State, Reg,
  /prebuilts/clang/host/darwin-x86/clang-4479392/include/clang/StaticAnalyzer/Core/PathSensitive/
DynamicTypeMap.h 40 const MemRegion *Reg);
43 ProgramStateRef setDynamicTypeInfo(ProgramStateRef State, const MemRegion *Reg,
48 const MemRegion *Reg, QualType NewTy,
50 return setDynamicTypeInfo(State, Reg,
  /prebuilts/clang/host/darwin-x86/clang-4579689/include/clang/StaticAnalyzer/Core/PathSensitive/
DynamicTypeMap.h 40 const MemRegion *Reg);
43 ProgramStateRef setDynamicTypeInfo(ProgramStateRef State, const MemRegion *Reg,
48 const MemRegion *Reg, QualType NewTy,
50 return setDynamicTypeInfo(State, Reg,
  /prebuilts/clang/host/darwin-x86/clang-4630689/include/clang/StaticAnalyzer/Core/PathSensitive/
DynamicTypeMap.h 40 const MemRegion *Reg);
43 ProgramStateRef setDynamicTypeInfo(ProgramStateRef State, const MemRegion *Reg,
48 const MemRegion *Reg, QualType NewTy,
50 return setDynamicTypeInfo(State, Reg,
  /prebuilts/clang/host/darwin-x86/clang-4639204/include/clang/StaticAnalyzer/Core/PathSensitive/
DynamicTypeMap.h 40 const MemRegion *Reg);
43 ProgramStateRef setDynamicTypeInfo(ProgramStateRef State, const MemRegion *Reg,
48 const MemRegion *Reg, QualType NewTy,
50 return setDynamicTypeInfo(State, Reg,
  /prebuilts/clang/host/darwin-x86/clang-4691093/include/clang/StaticAnalyzer/Core/PathSensitive/
DynamicTypeMap.h 40 const MemRegion *Reg);
43 ProgramStateRef setDynamicTypeInfo(ProgramStateRef State, const MemRegion *Reg,
48 const MemRegion *Reg, QualType NewTy,
50 return setDynamicTypeInfo(State, Reg,
  /prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
DynamicTypeMap.h 40 const MemRegion *Reg);
43 ProgramStateRef setDynamicTypeInfo(ProgramStateRef State, const MemRegion *Reg,
48 const MemRegion *Reg, QualType NewTy,
50 return setDynamicTypeInfo(State, Reg,
  /prebuilts/clang/host/linux-x86/clang-4393122/include/clang/StaticAnalyzer/Core/PathSensitive/
DynamicTypeMap.h 40 const MemRegion *Reg);
43 ProgramStateRef setDynamicTypeInfo(ProgramStateRef State, const MemRegion *Reg,
48 const MemRegion *Reg, QualType NewTy,
50 return setDynamicTypeInfo(State, Reg,

Completed in 500 milliseconds

1 2 3 4 5 6 7 8 91011>>