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    Searched refs:RegRead (Results 1 - 9 of 9) sorted by null

  /device/linaro/bootloader/edk2/SecurityPkg/Library/TpmCommLib/
TisPc.c 30 UINT8 RegRead;
32 RegRead = MmioRead8 ((UINTN)&TisReg->Access);
33 return (BOOLEAN)(RegRead != (UINT8)-1);
56 UINT8 RegRead;
60 RegRead = MmioRead8 ((UINTN)Register);
61 if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0)
  /device/linaro/bootloader/edk2/SecurityPkg/Library/Tpm12DeviceLibDTpm/
Tpm12Tis.c 54 UINT8 RegRead;
56 RegRead = MmioRead8 ((UINTN)&TisReg->Access);
57 return (BOOLEAN)(RegRead != (UINT8)-1);
117 UINT8 RegRead;
121 RegRead = MmioRead8 ((UINTN)Register);
122 if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0)
481 UINT32 RegRead;
485 RegRead = MmioRead32 ((UINTN)Register);
486 if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0) {
    [all...]
  /device/linaro/bootloader/edk2/SecurityPkg/Library/Tpm2DeviceLibDTpm/
Tpm2Tis.c 48 UINT8 RegRead;
50 RegRead = MmioRead8 ((UINTN)&TisReg->Access);
51 return (BOOLEAN)(RegRead != (UINT8)-1);
73 UINT8 RegRead;
77 RegRead = MmioRead8 ((UINTN)Register);
78 if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0)
Tpm2Ptp.c 59 UINT8 RegRead;
61 RegRead = MmioRead8 ((UINTN)Reg);
62 if (RegRead == 0xFF) {
90 UINT32 RegRead;
94 RegRead = MmioRead32 ((UINTN)Register);
95 if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0) {
  /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/
PcieInitLib.c 52 RegRead((UINT64)mPcieIntCfg.RegResource[Port] + Offset, Value);
64 RegRead((UINT64)mPcieIntCfg.CfgResource[Port] + Offset0 + Offset1, Value);
78 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_CLKREQ_REG, pcie0.UInt32);
83 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE1_CLKREQ_REG, pcie1.UInt32);
88 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE2_CLKREQ_REG, pcie2.UInt32);
93 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_CLKREQ_REG, pcie3.UInt32);
121 RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0xf4 + Laneid * 0x4, Value);
138 RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i * 0x4, Value);
144 RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i * 0x4, Value);
164 RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value);
    [all...]
PcieInitLib.h 74 #define RegRead(addr,data) ((data) = MmioRead32 (addr))
  /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/
PcieInitLib.c 51 RegRead((UINT64)mPcieIntCfg.RegResource[Port] + Offset, Value);
63 RegRead((UINT64)mPcieIntCfg.CfgResource[Port] + Offset0 + Offset1, Value);
77 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_CLKREQ_REG, pcie0.UInt32);
82 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE1_CLKREQ_REG, pcie1.UInt32);
87 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE2_CLKREQ_REG, pcie2.UInt32);
92 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_CLKREQ_REG, pcie3.UInt32);
563 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_ST_REG, pcs_local_reset_status);
577 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_ST_REG, hilink_reset_status);
611 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_ST_REG, pcs_local_status);
622 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_ST_REG, hilink_reset_stat (…)
    [all...]
PcieInitLib.h 69 #define RegRead(addr,data) ((data) = *(volatile UINT32*)(UINTN)(addr))
  /device/linaro/bootloader/edk2/QuarkPlatformPkg/Library/Tpm12DeviceLibInfineonI2c/
TisPc.c 299 UINT8 RegRead;
303 RegRead = TpmReadByte (Register);
304 if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0)

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