| /external/llvm/lib/Target/AMDGPU/ |
| R600RegisterInfo.cpp | 29 BitVector Reserved(getNumRegs());
34 Reserved.set(AMDGPU::ZERO);
35 Reserved.set(AMDGPU::HALF);
36 Reserved.set(AMDGPU::ONE);
37 Reserved.set(AMDGPU::ONE_INT);
38 Reserved.set(AMDGPU::NEG_HALF);
39 Reserved.set(AMDGPU::NEG_ONE);
40 Reserved.set(AMDGPU::PV_X);
41 Reserved.set(AMDGPU::ALU_LITERAL_X);
42 Reserved.set(AMDGPU::ALU_CONST)
[all...] |
| /device/linaro/bootloader/edk2/MdePkg/Include/IndustryStandard/ |
| MemoryMappedConfigurationSpaceAccessTable.h | 6 Copyright (c) 2007 - 2008, Intel Corporation. All rights reserved.<BR>
34 UINT32 Reserved;
43 UINT64 Reserved;
|
| LowPowerIdleTable.h | 4 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
44 UINT32 Reserved : 30; ///< Reserved for future use. Must be zero
59 UINT8 Reserved[2]; ///< Must be Zero
|
| DmaRemappingReportingTable.h | 5 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
111 - Bits[7:1] Reserved.
114 UINT8 Reserved;
126 Reserved Memory Region Reporting Structure (RMRR) is described in section 8.4
127 Reserved memory ranges that may be DMA targets may be reported through the
129 reserved memory region.
133 UINT8 Reserved[2];
140 /// Base address of 4KB-aligned reserved memory region
144 Last address of the reserved memory region. Value in this field must be
145 greater than the value in Reserved Memory Region Base Address field.
[all...] |
| IpmiNetFnChassis.h | 10 Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
122 UINT8 Reserved:4;
150 UINT8 Reserved:1;
171 UINT8 Reserved[3];
179 UINT8 Reserved: 6;
189 UINT8 Reserved: 5;
194 UINT8 Reserved: 3;
238 UINT8 Reserved:4;
262 UINT8 Reserved:4;
278 UINT8 Reserved:4;
[all...] |
| PciExpress31.h | 6 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
34 UINT32 Reserved : 3;
50 UINT32 Reserved : 4;
62 UINT32 Reserved : 1;
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/ |
| McfgTable.h | 3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
65 UINT32 Reserved;
74 UINT64 Reserved;
|
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/x86_64-w64-mingw32/include/ |
| mpeg2bits.h | 12 WORD Reserved :2;
20 BYTE Reserved :2;
|
| /external/llvm/lib/Target/Mips/ |
| MipsRegisterInfo.cpp | 163 BitVector Reserved(getNumRegs());
168 Reserved.set(ReservedGPR32[I]);
172 Reserved.set(Mips::T6); // Reserved for control flow mask.
173 Reserved.set(Mips::T7); // Reserved for memory access mask.
174 Reserved.set(Mips::T8); // Reserved for thread pointer.
178 Reserved.set(ReservedGPR64[I]);
182 Reserved.set(Mips::GP)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| SystemZRegisterInfo.cpp | 54 BitVector Reserved(getNumRegs());
59 Reserved.set(SystemZ::R11D);
60 Reserved.set(SystemZ::R11W);
61 Reserved.set(SystemZ::R10P);
62 Reserved.set(SystemZ::R10Q);
65 Reserved.set(SystemZ::R14D);
66 Reserved.set(SystemZ::R15D);
67 Reserved.set(SystemZ::R14W);
68 Reserved.set(SystemZ::R15W);
69 Reserved.set(SystemZ::R14P)
[all...] |
| /device/linaro/bootloader/edk2/BaseTools/Source/C/Include/IndustryStandard/ |
| MemoryMappedConfigurationSpaceAccessTable.h | 6 Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
35 UINT32 Reserved;
|
| EfiPci.h | 4 Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
30 UINT8 Reserved[4];
43 UINT8 Reserved[8];
|
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/ |
| MemoryMappedConfigurationSpaceAccessTable.h | 3 Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>
46 UINT32 Reserved;
|
| /device/linaro/bootloader/edk2/UefiCpuPkg/Include/ |
| CpuHotPlugData.h | 4 Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
28 UINT32 Reserved;
|
| /device/linaro/bootloader/edk2/BaseTools/Source/C/Include/Common/ |
| VariableFormat.h | 4 Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
34 UINT16 Reserved;
41 UINT8 Reserved;
|
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| PTXRegisterInfo.h | 42 BitVector Reserved(getNumRegs());
43 return Reserved; // reserve no regs
|
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 43 BitVector Reserved(getNumRegs());
44 // FIXME: G1 reserved for now for large imm generation by frame code.
45 Reserved.set(SP::G1);
46 Reserved.set(SP::G2);
47 Reserved.set(SP::G3);
48 Reserved.set(SP::G4);
49 Reserved.set(SP::O6);
50 Reserved.set(SP::I6);
51 Reserved.set(SP::I7);
52 Reserved.set(SP::G0)
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 56 BitVector Reserved(getNumRegs());
58 // FIXME: G1 reserved for now for large imm generation by frame code.
59 Reserved.set(SP::G1);
63 Reserved.set(SP::G2);
64 Reserved.set(SP::G3);
65 Reserved.set(SP::G4);
67 // G5 is not reserved in 64 bit mode.
69 Reserved.set(SP::G5);
71 Reserved.set(SP::O6);
72 Reserved.set(SP::I6)
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Pv660/Pv660AcpiTables/ |
| Iort.asl | 21 [0004] Reserved : 00000000
28 [0004] Reserved : 00000000
39 [0004] Reserved : 00000000
50 [0004] Reserved : 00000000
61 [0004] Reserved : 00000000
72 [0004] Reserved : 00000000
84 [0002] Reserved : 0000
103 [0004] Reserved : 00000000
115 [0002] Reserved : 0000
134 [0004] Reserved : 00000000
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/ |
| D03Iort.asl | 21 [0004] Reserved : 00000000
28 [0004] Reserved : 00000000
39 [0004] Reserved : 00000000
51 [0002] Reserved : 0000
70 [0004] Reserved : 00000000
82 [0002] Reserved : 0000
101 [0004] Reserved : 00000000
113 [0002] Reserved : 0000
132 [0004] Reserved : 00000000
144 [0002] Reserved : 0000
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.cpp | 75 BitVector Reserved(getNumRegs());
78 // Mark 4 special registers with subregisters as reserved.
79 Reserved.set(MSP430::PCB);
80 Reserved.set(MSP430::SPB);
81 Reserved.set(MSP430::SRB);
82 Reserved.set(MSP430::CGB);
83 Reserved.set(MSP430::PC);
84 Reserved.set(MSP430::SP);
85 Reserved.set(MSP430::SR);
86 Reserved.set(MSP430::CG)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| MBlazeRegisterInfo.cpp | 72 BitVector Reserved(getNumRegs());
73 Reserved.set(MBlaze::R0);
74 Reserved.set(MBlaze::R1);
75 Reserved.set(MBlaze::R2);
76 Reserved.set(MBlaze::R13);
77 Reserved.set(MBlaze::R14);
78 Reserved.set(MBlaze::R15);
79 Reserved.set(MBlaze::R16);
80 Reserved.set(MBlaze::R17);
81 Reserved.set(MBlaze::R18)
[all...] |
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Include/ |
| EfiFlashMap.h | 3 Copyright (c) 2004 - 2007, Intel Corporation. All rights reserved.<BR>
43 #define EFI_FLASH_AREA_RESERVED_03 0x3 // Reserved for backwards compatibility
44 #define EFI_FLASH_AREA_RESERVED_04 0x4 // Reserved for backwards compatibility
47 #define EFI_FLASH_AREA_RESERVED_07 0x7 // Reserved for backwards compatibility
48 #define EFI_FLASH_AREA_RESERVED_08 0x8 // Reserved for backwards compatibility
49 #define EFI_FLASH_AREA_RESERVED_09 0x9 // Reserved for backwards compatibility
50 #define EFI_FLASH_AREA_RESERVED_0A 0x0a // Reserved for backwards compatibility
65 UINT32 Reserved;
72 UINT8 Reserved[3];
80 UINT8 Reserved[3];
[all...] |
| EfiPci.h | 3 Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
37 UINT8 Reserved[4];
50 UINT8 Reserved[8];
|
| /bootable/recovery/tools/recovery_l10n/ |
| Android.mk | 1 # Copyright 2012 Google Inc. All Rights Reserved.
|
