| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/msp430/ |
| errata_warns.l | 9 [^:]*:18: Warning: CPU11: PC is destinstion of SR altering instruction
10 [^:]*:19: Warning: CPU11: PC is destinstion of SR altering instruction
11 [^:]*:20: Warning: CPU11: PC is destinstion of SR altering instruction
13 [^:]*:21: Warning: CPU11: PC is destinstion of SR altering instruction
14 [^:]*:22: Warning: CPU11: PC is destinstion of SR altering instruction
15 [^:]*:23: Warning: CPU11: PC is destinstion of SR altering instruction
16 [^:]*:24: Warning: CPU11: PC is destinstion of SR altering instruction
17 [^:]*:25: Warning: CPU11: PC is destinstion of SR altering instruction
18 [^:]*:26: Warning: CPU11: PC is destinstion of SR altering instruction
19 [^:]*:30: Warning: CPU11: PC is destinstion of SR altering instructio
[all...] |
| bad.s | 32 BIC #8, SR
33 BIS #8, SR
34 MOV.W #1, SR
|
| errata_fixes.s | 8 # CPU11: The SR flags can be left in a bogus state after writing to the PC
9 # Instructions that do not set the SR flags are unaffected.
|
| /external/valgrind/coregrind/m_syswrap/ |
| priv_syswrap-linux-variants.h | 43 #define SR SysRes
52 #undef SR
|
| /external/elfutils/backends/ |
| x86_64_corenote.c | 54 #define SR(at, n, dwreg) \
73 SR (17,1, 51), /* %cs */
76 SR (20,1, 52), /* %ss */
78 SR (23,1, 53), /* %ds */
79 SR (24,1, 50), /* %es */
80 SR (25,2, 54), /* %fs-%gs */
83 #undef SR
|
| i386_corenote.c | 47 #define SR(at, n, dwreg) \
55 SR (7, 1, 43), /* %ds */
56 SR (8, 1, 40), /* %es */
57 SR (9, 1, 44), /* %fs */
58 SR (10, 1, 45), /* %gs */
61 SR (13, 1, 41), /* %cs */
64 SR (16, 1, 42), /* %ss */
67 #undef SR
|
| /external/llvm/lib/CodeGen/ |
| RenameIndependentSubregs.cpp | 69 LiveInterval::SubRange *SR;
72 SubRangeInfo(LiveIntervals &LIS, LiveInterval::SubRange &SR,
74 : ConEQ(LIS), SR(&SR), Index(Index) {}
161 for (LiveInterval::SubRange &SR : LI.subranges()) {
162 SubRangeInfos.push_back(SubRangeInfo(*LIS, SR, NumComponents));
165 unsigned NumSubComponents = ConEQ.Classify(SR);
186 const LiveInterval::SubRange &SR = *SRInfo.SR;
187 if ((SR.LaneMask & LaneMask) == 0
[all...] |
| VirtRegMap.cpp | 254 for (const LiveInterval::SubRange &SR : LI.subranges()) {
255 SubRanges.push_back(std::make_pair(&SR, SR.begin()));
256 if (!First.isValid() || SR.segments.front().start < First)
257 First = SR.segments.front().start;
258 if (!Last.isValid() || SR.segments.back().end > Last)
259 Last = SR.segments.back().end;
271 const LiveInterval::SubRange *SR = RangeIterPair.first;
273 while (SRI != SR->end() && SRI->end <= MBBBegin)
275 if (SRI == SR->end()
[all...] |
| MachineCopyPropagation.cpp | 90 for (MCSubRegIterator SR(Reg, &TRI, true); SR.isValid(); ++SR)
91 Map.erase(*SR);
239 for (MCSubRegIterator SR(Def, TRI, /*IncludeSelf=*/true); SR.isValid();
240 ++SR) {
241 CopyMap[*SR] = MI;
242 AvailCopyMap[*SR] = MI;
|
| /toolchain/binutils/binutils-2.27/opcodes/ |
| rx-decode.opc | 114 #define SR(r) OP (1, RX_Operand_Register, r, 0)
332 ID(mov); sBWL(sz); DIs(dst, dsp*4+a*2+b, sz); SR(src); F_____;
344 ID(mov); sBWL (sz); SR(rsrc); F_____;
365 ID(popm); SR(dsta); S2R(dstb); F_____;
368 ID(pushm); SR(dsta); S2R(dstb); F_____;
374 ID(mov); BWL(sz); OP(0, RX_Operand_Predec, 0, 0); SR(rsrc); F_____;
422 ID(and); DR(rdst); SR(srcb); S2R(srca); F__SZ_;
440 ID(or); DR(rdst); SR(srcb); S2R(srca); F__SZ_;
458 ID(xor); DR(rdst); SR(rdst); S2C(~0); F__SZ_;
461 ID(xor); DR(rdst); SR(rsrc); S2C(~0); F__SZ_
[all...] |
| m32r-opc.c | 222 /* add $dr,$sr */
225 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
228 /* add3 $dr,$sr,$hash$slo16 */
231 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } },
234 /* and $dr,$sr */
237 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
240 /* and3 $dr,$sr,$uimm16 */
243 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
246 /* or $dr,$sr */
249 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }
[all...] |
| rl78-decode.opc | 119 #define SR(r) OP (1, RL78_Operand_Register, RL78_Reg_##r, 0)
126 #define SCY() SR(PSW); SB(0)
225 ID(add); DRB(reg); SR(A); Fzac;
254 ID(addc); DRB(reg); SR(A); Fzac;
306 ID(and); DRB(reg); SR(A); Fz;
320 ID(and); DCY(); SR(A); SB(bit);
334 ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(C);
337 ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(NC);
340 ID(branch_cond); DC(pc+IMMS(1)+3); SR(None); COND(H);
343 ID(branch_cond); DC(pc+IMMS(1)+3); SR(None); COND(NH)
[all...] |
| /compatibility/cdd/8_performance-and-power/ |
| 8_4_power-consumption-accounting.md | 10 * [SR] STRONGLY RECOMMENDED to provide a per-component power profile
15 * [SR] STRONGLY RECOMMENDED to report all power consumption values in milliampere
17 * [SR] STRONGLY RECOMMENDED to report CPU power consumption per each process's UID.
20 * [SR] STRONGLY RECOMMENDED to make this power usage available via the
|
| /device/google/contexthub/firmware/os/platform/stm32/flash_script/ |
| tool.c | 24 volatile uint32_t SR;
54 while (FLASH->SR & 0x00010000);
|
| /external/clang/lib/StaticAnalyzer/Core/ |
| DynamicTypeMap.cpp | 34 if (const SymbolicRegion *SR = dyn_cast<SymbolicRegion>(Reg)) {
35 SymbolRef Sym = SR->getSymbol();
|
| /prebuilts/go/darwin-x86/test/fixedbugs/bug345.dir/ |
| io.go | 15 func SR(*SectionReader) {}
|
| /prebuilts/go/linux-x86/test/fixedbugs/bug345.dir/ |
| io.go | 15 func SR(*SectionReader) {}
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| DwarfExpression.cpp | 104 for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
105 Reg = TRI.getDwarfRegNum(*SR, false);
107 unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
137 for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
138 unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
141 Reg = TRI.getDwarfRegNum(*SR, false)
[all...] |
| /compatibility/cdd/5_multimedia/ |
| 5_6_audio-latency.md | 45 * [SR] Cold output latency of 100 milliseconds or less
46 * [SR] Continuous output latency of 45 milliseconds or less
47 * [SR] Minimize the cold output jitter
54 * [SR] STRONGLY RECOMMENDED to report low latency audio by declaring
56 * [SR] STRONGLY RECOMMENDED to also meet the requirements for low-latency
67 * [SR] Cold input latency of 100 milliseconds or less
68 * [SR] Continuous input latency of 30 milliseconds or less
69 * [SR] Continuous round-trip latency of 50 milliseconds or less
70 * [SR] Minimize the cold input jitte
|
| /external/llvm/lib/Target/Hexagon/ |
| RDFCopy.cpp | 67 RegisterRef SR = { I.Reg, I.SubReg };
68 EM.insert(std::make_pair(DR, SR));
187 RegisterRef SR = FR->second;
188 if (DR == SR)
191 auto &RDefSR = RDefMap[SR];
213 << " with " << Print<RegisterRef>(SR, DFG) << " in "
217 Op.setReg(SR.Reg);
218 Op.setSubReg(SR.Sub);
241 J.second = SR;
|
| /external/clang/include/clang/AST/ |
| RawCommentList.h | 43 RawComment(const SourceManager &SourceMgr, SourceRange SR,
147 RawComment(SourceRange SR, CommentKind K, bool IsTrailingComment,
150 Range(SR), RawTextValid(false), BriefTextValid(false), Kind(K),
|
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| CastSizeChecker.cpp | 108 const SymbolicRegion *SR = dyn_cast<SymbolicRegion>(R);
109 if (!SR)
113 SVal extent = SR->getExtent(svalBuilder);
|
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/clang/include/clang/AST/ |
| RawCommentList.h | 43 RawComment(const SourceManager &SourceMgr, SourceRange SR,
147 RawComment(SourceRange SR, CommentKind K, bool IsTrailingComment,
150 Range(SR), RawTextValid(false), BriefTextValid(false), Kind(K),
|
| /prebuilts/clang/host/darwin-x86/clang-4393122/include/clang/AST/ |
| RawCommentList.h | 43 RawComment(const SourceManager &SourceMgr, SourceRange SR,
147 RawComment(SourceRange SR, CommentKind K, bool IsTrailingComment,
150 Range(SR), RawTextValid(false), BriefTextValid(false), Kind(K),
|
| /prebuilts/clang/host/darwin-x86/clang-4479392/include/clang/AST/ |
| RawCommentList.h | 43 RawComment(const SourceManager &SourceMgr, SourceRange SR,
147 RawComment(SourceRange SR, CommentKind K, bool IsTrailingComment,
150 Range(SR), RawTextValid(false), BriefTextValid(false), Kind(K),
|
