| /external/llvm/lib/Target/Lanai/ |
| LanaiAluCode.h | 37 SRL = 0x27,
95 case SRL:
114 .Case("srl", SRL)
137 case ISD::SRL:
138 return AluCode::SRL;
|
| /bionic/libc/arch-mips/string/ |
| strcmp.S | 51 # define SRL dsrl
58 # define SRL srl
196 SRL $v0, $t2; \
212 SRL $a3, $t3
245 SRL $t0, $v0, POS; \
246 SRL $t1, $v1, POS; \
252 SRL $t8, $v0, POS; \
253 SRL $t9, $v1, POS; \
292 SRL $t8, $v0, 2
[all...] |
| strncmp.S | 53 # define SRL dsrl
61 # define SRL srl
131 srl $t0, $a2, (2 + NSIZE / 4)
277 SRL $t0, $v0, POS; \
278 SRL $t1, $v1, POS; \
284 SRL $t8, $v0, POS; \
285 SRL $t9, $v1, POS; \
324 SRL $t8, $v0, 24
325 SRL $t9, $v1, 2
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 27 case ISD::SRL: return ARM_AM::lsr;
|
| /external/libffi/src/mips/ |
| ffitarget.h | 152 # define SRL srl
159 # define SRL dsrl
|
| n32.S | 120 SRL t4, t6, 1*FFI_FLAG_BITS
131 SRL t4, t6, 2*FFI_FLAG_BITS
142 SRL t4, t6, 3*FFI_FLAG_BITS
153 SRL t4, t6, 4*FFI_FLAG_BITS
164 SRL t4, t6, 5*FFI_FLAG_BITS
175 SRL t4, t6, 6*FFI_FLAG_BITS
186 SRL t4, t6, 7*FFI_FLAG_BITS
206 SRL t6, 8*FFI_FLAG_BITS
|
| /external/python/cpython2/Modules/_ctypes/libffi/src/mips/ |
| ffitarget.h | 152 # define SRL srl
159 # define SRL dsrl
|
| n32.S | 120 SRL t4, t6, 1*FFI_FLAG_BITS
131 SRL t4, t6, 2*FFI_FLAG_BITS
142 SRL t4, t6, 3*FFI_FLAG_BITS
153 SRL t4, t6, 4*FFI_FLAG_BITS
164 SRL t4, t6, 5*FFI_FLAG_BITS
175 SRL t4, t6, 6*FFI_FLAG_BITS
186 SRL t4, t6, 7*FFI_FLAG_BITS
206 SRL t6, 8*FFI_FLAG_BITS
|
| /external/python/cpython3/Modules/_ctypes/libffi/src/mips/ |
| ffitarget.h | 152 # define SRL srl
159 # define SRL dsrl
|
| n32.S | 120 SRL t4, t6, 1*FFI_FLAG_BITS
131 SRL t4, t6, 2*FFI_FLAG_BITS
142 SRL t4, t6, 3*FFI_FLAG_BITS
153 SRL t4, t6, 4*FFI_FLAG_BITS
164 SRL t4, t6, 5*FFI_FLAG_BITS
175 SRL t4, t6, 6*FFI_FLAG_BITS
186 SRL t4, t6, 7*FFI_FLAG_BITS
206 SRL t6, 8*FFI_FLAG_BITS
|
| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 28 case ISD::SRL: return ARM_AM::lsr;
|
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 102 // normally expanded to the sequence SRA + SRL + ADD + SRA.
136 { ISD::SRL, MVT::v16i32, 1 },
139 { ISD::SRL, MVT::v8i64, 1 },
152 { ISD::SRL, MVT::v4i32, 1 },
155 { ISD::SRL, MVT::v8i32, 1 },
158 { ISD::SRL, MVT::v2i64, 1 },
160 { ISD::SRL, MVT::v4i64, 1 },
179 { ISD::SRL, MVT::v16i8, 2 },
182 { ISD::SRL, MVT::v8i16, 2 },
185 { ISD::SRL, MVT::v4i32, 2 }
[all...] |
| /prebuilts/go/darwin-x86/src/cmd/internal/obj/arm/ |
| anames.go | 82 "SRL",
|
| /prebuilts/go/darwin-x86/src/cmd/internal/obj/mips/ |
| anames.go | 87 "SRL",
|
| /prebuilts/go/linux-x86/src/cmd/internal/obj/arm/ |
| anames.go | 82 "SRL",
|
| /prebuilts/go/linux-x86/src/cmd/internal/obj/mips/ |
| anames.go | 87 "SRL",
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZSelectionDAGInfo.cpp | 176 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i32, IPM,
178 SDValue ROTL = DAG.getNode(ISD::ROTL, DL, MVT::i32, SRL,
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 156 case ISD::SRL:
303 // Make sure that the SINT_TO_FP and SRL instructions are available.
305 !TLI.isOperationLegalOrCustom(ISD::SRL, VT))
325 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
|
| LegalizeIntegerTypes.cpp | 74 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
270 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
561 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
661 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 87 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
320 ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
333 ISD::SRL, dl, NVT, DAG.getNode(ISD::BITREVERSE, dl, NVT, Op),
689 return DAG.getNode(ISD::SRL, SDLoc(N), LHS.getValueType(), LHS, RHS);
788 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| ISDOpcodes.h | 317 SHL, SRA, SRL, ROTL, ROTR,
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL
|
| /external/pcre/dist2/src/sljit/ |
| sljitNativeSPARC_32.c | 71 return push_inst(compiler, (op == SLJIT_MOV_S16 ? SRA : SRL) | D(dst) | S1(dst) | IMM(16), DR(dst));
130 FAIL_IF(push_inst(compiler, SRL | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst)));
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 351 } else if (Opcode == ISD::SRL) {
398 Op0.getOperand(0).getOpcode() == ISD::SRL) {
400 Op1.getOperand(0).getOpcode() != ISD::SRL) {
406 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
408 Op1.getOperand(0).getOpcode() != ISD::SRL) {
419 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
426 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
[all...] |
