| /art/runtime/arch/arm/ |
| registers_arm.h | 57 enum SRegister {
93 std::ostream& operator<<(std::ostream& os, const SRegister& rhs);
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| registers_arm.cc | 37 std::ostream& operator<<(std::ostream& os, const SRegister& rhs) {
41 os << "SRegister[" << static_cast<int>(rhs) << "]";
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| /art/compiler/optimizing/ |
| common_arm.h | 45 inline dwarf::Reg DWARFReg(vixl::aarch32::SRegister reg) {
64 inline vixl::aarch32::SRegister LowSRegisterFrom(Location location) {
66 return vixl::aarch32::SRegister(location.AsFpuRegisterPairLow<vixl::aarch32::SRegister>());
69 inline vixl::aarch32::SRegister HighSRegisterFrom(Location location) {
71 return vixl::aarch32::SRegister(location.AsFpuRegisterPairHigh<vixl::aarch32::SRegister>());
91 inline vixl::aarch32::SRegister SRegisterFrom(Location location) {
93 return vixl::aarch32::SRegister(location.reg());
96 inline vixl::aarch32::SRegister OutputSRegister(HInstruction* instr)
[all...] |
| code_generator_arm_vixl.h | 52 static const vixl::aarch32::SRegister kParameterFpuRegistersVIXL[] = {
102 static const vixl::aarch32::SRegister kRuntimeParameterFpuRegistersVIXL[] = {
144 : public CallingConvention<vixl::aarch32::Register, vixl::aarch32::SRegister> {
158 : public CallingConvention<vixl::aarch32::Register, vixl::aarch32::SRegister> {
[all...] |
| /art/compiler/utils/arm/ |
| managed_register_arm.h | 67 // [R..S[ single precision VFP registers (enum SRegister)
78 // [R..S[ single precision VFP registers (enum SRegister)
90 // (enum SRegister), or a VFP double precision register (enum DRegister).
105 constexpr SRegister AsSRegister() const {
107 return static_cast<SRegister>(id_ - kNumberOfCoreRegIds);
110 vixl::aarch32::SRegister AsVIXLSRegister() const {
112 return vixl::aarch32::SRegister(id_ - kNumberOfCoreRegIds);
125 constexpr SRegister AsOverlappingDRegisterLow() const {
128 return static_cast<SRegister>(d_reg * 2);
131 constexpr SRegister AsOverlappingDRegisterHigh() const
[all...] |
| managed_register_arm.cc | 37 SRegister low = AsOverlappingDRegisterLow();
38 SRegister high = AsOverlappingDRegisterHigh();
39 SRegister other_sreg = other.AsSRegister();
57 low = (r * 2) + kNumberOfCoreRegIds; // Return a SRegister.
84 os << "SRegister: " << static_cast<int>(AsSRegister());
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| assembler_arm_vixl.h | 206 void StoreSToOffset(vixl32::SRegister source, vixl32::Register base, int32_t offset);
214 void LoadSFromOffset(vixl32::SRegister reg, vixl32::Register base, int32_t offset);
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| assembler_arm_vixl.cc | 359 void ArmVIXLAssembler::StoreSToOffset(vixl32::SRegister source,
371 void ArmVIXLAssembler::LoadSFromOffset(vixl32::SRegister reg,
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| /art/compiler/utils/arm64/ |
| managed_register_arm64.h | 41 // [D..S[ single precision VFP registers (enum SRegister)
54 // * VFP single precision register (enum SRegister)
75 constexpr SRegister AsSRegister() const {
77 return static_cast<SRegister>(id_ - kNumberOfXRegIds - kNumberOfWRegIds -
92 constexpr SRegister AsOverlappingSRegister() const {
94 return static_cast<SRegister>(AsDRegister());
164 static constexpr Arm64ManagedRegister FromSRegister(SRegister r) {
177 static constexpr Arm64ManagedRegister FromSRegisterD(SRegister r) {
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| jni_macro_assembler_arm64.h | 211 void StoreSToOffset(SRegister source, XRegister base, int32_t offset);
223 void LoadSFromOffset(SRegister dest, XRegister base, int32_t offset);
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| /external/swiftshader/third_party/subzero/src/DartARM32/ |
| assembler_arm.h | 622 void vmovsr(SRegister sn, Register rt, Condition cond = AL);
624 void vmovrs(Register rt, SRegister sn, Condition cond = AL);
626 void vmovsrr(SRegister sm, Register rt, Register rt2, Condition cond = AL);
627 void vmovrrs(Register rt, Register rt2, SRegister sm, Condition cond = AL);
636 void vmovs(SRegister sd, SRegister sm, Condition cond = AL);
645 bool vmovs(SRegister sd, float s_imm, Condition cond = AL);
650 void vldrs(SRegister sd, Address ad, Condition cond = AL);
652 void vstrs(SRegister sd, Address ad, Condition cond = AL);
662 SRegister first, SRegister last, Condition cond = AL)
[all...] |
| assembler_arm.cc | 609 void Assembler::vmovsr(SRegister sn, Register rt, Condition cond) {
625 void Assembler::vmovrs(Register rt, SRegister sn, Condition cond) {
642 void Assembler::vmovsrr(SRegister sm, Register rt, Register rt2,
664 void Assembler::vmovrrs(Register rt, Register rt2, SRegister sm,
749 void Assembler::vldrs(SRegister sd, Address ad, Condition cond) {
762 void Assembler::vstrs(SRegister sd, Address ad, Condition cond) {
805 SRegister start,
851 SRegister first, SRegister last, Condition cond) {
859 SRegister first, SRegister last, Condition cond)
[all...] |
| /external/vixl/src/aarch32/ |
| disasm-aarch32.h | 342 virtual DisassemblerStream& operator<<(SRegister reg) {
[all...] |
| assembler-aarch32.h | 380 SRegister rd,
381 SRegister rm);
383 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
400 SRegister rd,
407 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm);
409 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm);
425 SRegister rd,
426 SRegister rm
[all...] |
| instructions-aarch32.cc | 79 SRegister VRegister::S() const {
81 return SRegister(GetCode());
148 SRegister VRegisterList::GetFirstAvailableSRegister() const {
150 if (((list_ >> i) & 0x1) != 0) return SRegister(i);
152 return SRegister();
157 SRegister first = reglist.GetFirstSRegister();
158 SRegister last = reglist.GetLastSRegister();
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| macro-assembler-aarch32.h | 733 void Vldr(Condition cond, DataType dt, SRegister rd, RawLiteral* literal) {
752 void Vldr(DataType dt, SRegister rd, RawLiteral* literal) {
755 void Vldr(Condition cond, SRegister rd, RawLiteral* literal) {
758 void Vldr(SRegister rd, RawLiteral* literal) {
791 void Vldr(Condition cond, SRegister rd, float v) {
799 void Vldr(SRegister rd, float v) { Vldr(al, rd, v); }
813 void Vmov(Condition cond, SRegister rt, float v) { Vmov(cond, F32, rt, v); }
814 void Vmov(SRegister rt, float v) { Vmov(al, F32, rt, v); }
[all...] |
| instructions-aarch32.h | 174 class SRegister;
184 SRegister S() const;
189 class SRegister : public VRegister {
191 SRegister() : VRegister(kNoRegister, 0, kSRegSizeInBits) {}
192 explicit SRegister(uint32_t code)
215 inline std::ostream& operator<<(std::ostream& os, const SRegister reg) {
224 SRegister GetLane(uint32_t lane) const {
228 return SRegister(GetCode() * lane_count + lane);
376 SRegister GetSLane(uint32_t lane) const {
380 return SRegister(GetCode() * lane_count + lane)
[all...] |
| disasm-aarch32.cc | [all...] |
| assembler-aarch32.cc | [all...] |
| /art/runtime/arch/arm64/ |
| registers_arm64.cc | 65 std::ostream& operator<<(std::ostream& os, const SRegister& rhs) {
69 os << "SRegister[" << static_cast<int>(rhs) << "]";
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| registers_arm64.h | 153 enum SRegister {
189 std::ostream& operator<<(std::ostream& os, const SRegister& rhs);
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| /external/vixl/test/aarch32/ |
| test-utils-aarch32.h | 142 // SRegister accessors
190 const SRegister& sreg);
198 bool EqualFP32(float expected, const RegisterDump* core, const SRegister& dreg);
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| test-utils-aarch32.cc | 127 const SRegister& sreg) {
209 const SRegister& sreg) {
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| /external/swiftshader/third_party/subzero/src/ |
| IceRegistersARM32.h | 54 enum SRegister {
175 static inline SRegister getEncodedSReg(RegNumT RegNum) {
177 return SRegister(RegTable[RegNum].Encoding);
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| /art/compiler/jni/quick/arm64/ |
| calling_convention_arm64.cc | 48 static const SRegister kSArgumentRegisters[] = {
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