| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.h | 26 inline static unsigned getCRFromCRBit(unsigned SrcReg) {
28 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
29 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
31 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
32 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
34 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT |
[all...] |
| PPCQPXLoadSplat.cpp | 88 unsigned SrcReg = SMI->getOperand(1).getReg();
90 if (MI->modifiesRegister(SrcReg, TRI)) {
105 if (SplatReg != SrcReg) {
109 TRI->getSubRegIndex(SrcReg, MI->getOperand(0).getReg());
115 MI->substituteRegister(SrcReg, SplatReg, 0, *TRI);
140 (SrcReg != SplatReg &&
|
| /external/llvm/lib/CodeGen/ |
| PHIEliminationUtils.h | 17 /// SrcReg when following the CFG edge to SuccMBB. This needs to be after
18 /// any def of SrcReg, but before any subsequent point where control flow
22 unsigned SrcReg);
|
| RegisterCoalescer.h | 36 unsigned SrcReg;
41 /// The sub-register index of the old SrcReg in the new coalesced register.
50 /// True when DstReg and SrcReg are reversed from the original
56 /// SrcReg and DstReg.
61 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0),
68 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
75 /// Swap SrcReg and DstReg. Return false if swapping is impossible
103 unsigned getSrcReg() const { return SrcReg; }
108 /// Return the subregister index that SrcReg will be coalesced into, or 0.
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| PHIEliminationUtils.h | 17 /// SrcReg when following the CFG edge to SuccMBB. This needs to be after
18 /// any def of SrcReg, but before any subsequent point where control flow
22 unsigned SrcReg);
|
| RegisterCoalescer.h | 36 /// SrcReg - the virtual register that will be coalesced into dstReg.
37 unsigned SrcReg;
39 /// subReg_ - The subregister index of srcReg in DstReg. It is possible the
40 /// coalesce SrcReg into a subreg of the larger DstReg when DstReg is a
50 /// Flipped - True when DstReg and SrcReg are reversed from the oriignal
60 : TII(tii), TRI(tri), DstReg(0), SrcReg(0), SubIdx(0),
67 /// flip - Swap SrcReg and DstReg. Return false if swapping is impossible
95 unsigned getSrcReg() const { return SrcReg; }
97 /// getSubIdx - Return the subregister index in DstReg that SrcReg will be
|
| /external/mesa3d/src/mesa/program/ |
| prog_opt_constant_fold.c | 39 if (inst->SrcReg[i].File != PROGRAM_CONSTANT)
41 if (inst->SrcReg[i].RelAddr)
140 get_value(prog, &inst->SrcReg[0], a);
141 get_value(prog, &inst->SrcReg[1], b);
149 inst->SrcReg[0] = src_reg_for_vec4(prog, result);
151 inst->SrcReg[1].File = PROGRAM_UNDEFINED;
152 inst->SrcReg[1].Swizzle = SWIZZLE_NOOP;
169 get_value(prog, &inst->SrcReg[0], a);
170 get_value(prog, &inst->SrcReg[1], b);
171 get_value(prog, &inst->SrcReg[2], c)
[all...] |
| prog_parameter_layout.c | 131 if (inst->SrcReg[i].Base.RelAddr) {
134 if (!inst->SrcReg[i].Symbol->pass1_done) {
137 inst->SrcReg[i].Symbol->param_binding_begin,
138 inst->SrcReg[i].Symbol->param_binding_length);
145 inst->SrcReg[i].Symbol->param_binding_begin = new_begin;
146 inst->SrcReg[i].Symbol->pass1_done = 1;
153 inst->Base.SrcReg[i] = inst->SrcReg[i].Base;
154 inst->Base.SrcReg[i].Index +=
155 inst->SrcReg[i].Symbol->param_binding_begin
[all...] |
| programopt.c | 93 newInst[i].SrcReg[0].File = PROGRAM_STATE_VAR;
94 newInst[i].SrcReg[0].Index = mvpRef[i];
95 newInst[i].SrcReg[0].Swizzle = SWIZZLE_NOOP;
96 newInst[i].SrcReg[1].File = PROGRAM_INPUT;
97 newInst[i].SrcReg[1].Index = VERT_ATTRIB_POS;
98 newInst[i].SrcReg[1].Swizzle = SWIZZLE_NOOP;
164 newInst[0].SrcReg[0].File = PROGRAM_INPUT;
165 newInst[0].SrcReg[0].Index = VERT_ATTRIB_POS;
166 newInst[0].SrcReg[0].Swizzle = SWIZZLE_XXXX;
167 newInst[0].SrcReg[1].File = PROGRAM_STATE_VAR
[all...] |
| prog_instruction.c | 46 inst[i].SrcReg[0].File = PROGRAM_UNDEFINED;
47 inst[i].SrcReg[0].Swizzle = SWIZZLE_NOOP;
48 inst[i].SrcReg[1].File = PROGRAM_UNDEFINED;
49 inst[i].SrcReg[1].Swizzle = SWIZZLE_NOOP;
50 inst[i].SrcReg[2].File = PROGRAM_UNDEFINED;
51 inst[i].SrcReg[2].Swizzle = SWIZZLE_NOOP;
221 if (inst->SrcReg[i].File == inst->DstReg.File &&
222 inst->SrcReg[i].Index == inst->DstReg.Index) {
228 GLuint swizzle = GET_SWZ(inst->SrcReg[i].Swizzle, chan);
|
| prog_execute.c | 301 inst->SrcReg[0].File == PROGRAM_INPUT &&
302 inst->SrcReg[0].Index == VARYING_SLOT_TEX0 + inst->TexSrcUnit) {
304 GLuint attr = inst->SrcReg[0].Index;
405 fetch_vector4(&inst->SrcReg[0], machine, a);
416 fetch_vector4(&inst->SrcReg[0], machine, a);
417 fetch_vector4(&inst->SrcReg[1], machine, b);
433 fetch_vector4(&inst->SrcReg[0], machine, t);
481 fetch_vector4(&inst->SrcReg[0], machine, a);
482 fetch_vector4(&inst->SrcReg[1], machine, b);
483 fetch_vector4(&inst->SrcReg[2], machine, c)
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_pair_translate.c | 44 inst->SrcReg[2] = inst->SrcReg[1];
45 inst->SrcReg[1].File = RC_FILE_NONE;
46 inst->SrcReg[1].Swizzle = RC_SWIZZLE_1111;
47 inst->SrcReg[1].Negate = RC_MASK_NONE;
51 tmp = inst->SrcReg[2];
52 inst->SrcReg[2] = inst->SrcReg[0];
53 inst->SrcReg[0] = tmp;
66 inst->SrcReg[1].File = RC_FILE_NONE
[all...] |
| radeon_optimize.c | 76 &reader_data->Writer->U.I.PreSub.SrcReg[0],
77 &reader_data->Writer->U.I.PreSub.SrcReg[1])) {
91 if(reader_data->Writer->U.I.SrcReg[0].File != RC_FILE_TEMPORARY &&
92 reader_data->Writer->U.I.SrcReg[0].File != RC_FILE_INPUT &&
166 inst->U.I.SrcReg[0].File == RC_FILE_PRESUB ||
167 inst->U.I.SrcReg[0].Abs ||
168 inst->U.I.SrcReg[0].Negate) {
177 *reader_data.Readers[i].U.I.Src = chain_srcregs(*reader_data.Readers[i].U.I.Src, inst_mov->U.I.SrcReg[0]);
179 if (inst_mov->U.I.SrcReg[0].File == RC_FILE_PRESUB)
232 if (is_src_uniform_constant(inst->U.I.SrcReg[2], &swz, &negate))
[all...] |
| radeon_program_tex.c | 70 inst_mov->U.I.SrcReg[0] = inst->U.I.SrcReg[0];
71 inst_mov->U.I.SrcReg[1].File = RC_FILE_CONSTANT;
72 inst_mov->U.I.SrcReg[1].Index =
76 reset_srcreg(&inst->U.I.SrcReg[0]);
77 inst->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
78 inst->U.I.SrcReg[0].Index = temp;
93 inst_rcp->U.I.SrcReg[0] = inst->U.I.SrcReg[0];
96 inst_rcp->U.I.SrcReg[0].Swizzle
[all...] |
| radeon_compiler.c | 125 if (inst->U.I.SrcReg[i].File == RC_FILE_INPUT)
126 c->Program.InputsRead |= 1 << inst->U.I.SrcReg[i].Index;
151 if (inst->U.I.SrcReg[i].File == RC_FILE_INPUT && inst->U.I.SrcReg[i].Index == input) {
152 inst->U.I.SrcReg[i].File = new_input.File;
153 inst->U.I.SrcReg[i].Index = new_input.Index;
154 inst->U.I.SrcReg[i].Swizzle = combine_swizzles(new_input.Swizzle, inst->U.I.SrcReg[i].Swizzle);
155 if (!inst->U.I.SrcReg[i].Abs) {
156 inst->U.I.SrcReg[i].Negate ^= new_input.Negate
[all...] |
| r3xx_vertprog.c | 43 (PVS_SRC_OPERAND(t_src_index(vp, &vpi->SrcReg[x]), \
48 t_src_class(vpi->SrcReg[x].File), \
49 RC_MASK_NONE) | (vpi->SrcReg[x].RelAddr << 4))
198 inst[1] = t_src(vp, &vpi->SrcReg[0]);
215 inst[1] = t_src(vp, &vpi->SrcReg[0]);
216 inst[2] = t_src(vp, &vpi->SrcReg[1]);
232 inst[1] = t_src_scalar(vp, &vpi->SrcReg[0]);
251 inst[1] = PVS_SRC_OPERAND(t_src_index(vp, &vpi->SrcReg[0]), t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 0)), // X
252 t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 3)), //
[all...] |
| radeon_emulate_loops.c | 100 if(!rc_src_reg_is_immediate(value->C, inst->U.I.SrcReg[0].File,
101 inst->U.I.SrcReg[0].Index)){
107 inst->U.I.SrcReg[0].Index,
108 inst->U.I.SrcReg[0].Swizzle,
109 inst->U.I.SrcReg[0].Negate, 0);
141 if(inst->U.I.SrcReg[0].File == RC_FILE_TEMPORARY &&
142 inst->U.I.SrcReg[0].Index == count_inst->Index &&
143 inst->U.I.SrcReg[0].Swizzle == count_inst->Swz){
145 } else if( inst->U.I.SrcReg[1].File == RC_FILE_TEMPORARY &&
146 inst->U.I.SrcReg[1].Index == count_inst->Index &
[all...] |
| radeon_vert_fc.c | 131 new_inst->U.I.SrcReg[0].Index = 0;
132 new_inst->U.I.SrcReg[0].File = RC_FILE_NONE;
133 new_inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_0000;
141 build_pred_src(&new_inst->U.I.SrcReg[0], fc_state);
151 new_inst->U.I.SrcReg[1].Index = 0;
152 new_inst->U.I.SrcReg[1].File = RC_FILE_NONE;
153 new_inst->U.I.SrcReg[1].Swizzle = RC_SWIZZLE_0000;
165 inst->U.I.SrcReg[0].Index = 0;
166 inst->U.I.SrcReg[0].File = RC_FILE_NONE;
167 inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_0000
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| BlackfinInstrInfo.cpp | 102 unsigned DestReg, unsigned SrcReg,
104 if (BF::ALLRegClass.contains(DestReg, SrcReg)) {
106 .addReg(SrcReg, getKillRegState(KillSrc));
110 if (BF::D16RegClass.contains(DestReg, SrcReg)) {
112 .addReg(SrcReg, getKillRegState(KillSrc))
118 if (SrcReg == BF::NCC) {
120 .addReg(SrcReg, getKillRegState(KillSrc));
124 if (SrcReg == BF::CC) {
126 .addReg(SrcReg, getKillRegState(KillSrc));
131 if (BF::DRegClass.contains(SrcReg)) {
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| Thumb1InstrInfo.cpp | 37 unsigned DestReg, unsigned SrcReg,
40 .addReg(SrcReg, getKillRegState(KillSrc)));
41 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
47 unsigned SrcReg, bool isKill, int FI,
51 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
52 isARMLowRegister(SrcReg))) && "Unknown regclass!");
55 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
56 isARMLowRegister(SrcReg))) {
69 .addReg(SrcReg, getKillRegState(isKill))
|
| Thumb1InstrInfo.h | 42 unsigned DestReg, unsigned SrcReg,
46 unsigned SrcReg, bool isKill, int FrameIndex,
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/tests/ |
| radeon_compiler_util_tests.c | 53 &replace_inst.U.I.SrcReg[0],
54 &add_inst.U.I.SrcReg[0], &add_inst.U.I.SrcReg[1]);
|
| /external/llvm/lib/Target/ARM/ |
| Thumb1InstrInfo.cpp | 43 unsigned SrcReg, bool KillSrc) const {
48 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
51 if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg)
54 .addReg(SrcReg, getKillRegState(KillSrc)));
64 .addReg(SrcReg, getKillRegState(KillSrc));
72 unsigned SrcReg, bool isKill, int FI,
76 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
77 isARMLowRegister(SrcReg))) && "Unknown regclass!");
80 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
81 isARMLowRegister(SrcReg))) {
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonPeephole.cpp | 143 unsigned SrcReg = Src.getReg();
146 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
150 PeepholeMap[DstReg] = SrcReg;
164 unsigned SrcReg = Src2.getReg();
165 PeepholeMap[DstReg] = SrcReg;
181 unsigned SrcReg = Src1.getReg();
183 std::make_pair(*&SrcReg, Hexagon::subreg_hireg);
192 unsigned SrcReg = Src.getReg();
195 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
199 PeepholeMap[DstReg] = SrcReg;
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 304 unsigned DestReg, unsigned SrcReg,
307 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
309 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
311 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
313 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
315 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
317 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
325 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
327 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc))
[all...] |
