| /external/vixl/test/aarch32/ |
| test-simulator-cond-rd-operand-rn-a32.cc | 126 M(Sxth) \
483 #include "aarch32/traces/simulator-cond-rd-operand-rn-sxth-a32.h"
|
| test-simulator-cond-rd-operand-rn-ror-amount-a32.cc | 118 M(Sxth) \
548 #include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-sxth-a32.h"
[all...] |
| test-simulator-cond-rd-operand-rn-ror-amount-t32.cc | 118 M(Sxth) \
548 #include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-sxth-t32.h"
[all...] |
| test-simulator-cond-rd-operand-rn-t32.cc | 126 M(Sxth) \
483 #include "aarch32/traces/simulator-cond-rd-operand-rn-sxth-t32.h"
|
| test-disasm-a32.cc | [all...] |
| /art/compiler/utils/arm64/ |
| jni_macro_assembler_arm64.cc | 511 ___ Sxth(reg_w(reg.AsWRegister()), reg_w(reg.AsWRegister()));
[all...] |
| /external/v8/src/arm64/ |
| macro-assembler-arm64-inl.h | 1151 void MacroAssembler::Sxth(const Register& rd, const Register& rn) {
1154 sxth(rd, rn);
[all...] |
| macro-assembler-arm64.h | 543 inline void Sxth(const Register& rd, const Register& rn);
[all...] |
| /external/v8/src/compiler/arm64/ |
| code-generator-arm64.cc | 121 return Operand(InputRegister32(index), SXTH);
151 return Operand(InputRegister64(index), SXTH);
[all...] |
| /art/compiler/optimizing/ |
| intrinsics_arm64.cc | 311 __ Sxth(WRegisterFrom(out), WRegisterFrom(out));
[all...] |
| /external/vixl/src/aarch64/ |
| macro-assembler-aarch64.h | [all...] |
| /external/vixl/src/aarch32/ |
| macro-assembler-aarch32.h | [all...] |
| /external/vixl/test/aarch64/ |
| test-assembler-aarch64.cc | 431 __ Mvn(x13, Operand(x2, SXTH, 3));
606 __ Mov(x26, Operand(x13, SXTH, 3));
660 __ Mov(w22, Operand(w11, SXTH, 1));
667 __ Mov(x28, Operand(x12, SXTH, 1));
743 __ Orr(x11, x0, Operand(x1, SXTH, 1));
837 __ Orn(x11, x0, Operand(x1, SXTH, 1));
904 __ And(x11, x0, Operand(x1, SXTH, 1));
1042 __ Bic(x11, x0, Operand(x1, SXTH, 1));
[all...] |
