| /external/llvm/lib/Target/SystemZ/ |
| SystemZCallingConv.cpp | 1 //===-- SystemZCallingConv.cpp - Calling conventions for SystemZ ----------===//
15 const MCPhysReg SystemZ::ArgGPRs[SystemZ::NumArgGPRs] = {
16 SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D
19 const MCPhysReg SystemZ::ArgFPRs[SystemZ::NumArgFPRs] =
[all...] |
| SystemZInstrInfo.cpp | 1 //===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
35 if (SystemZ::GRH32BitRegClass.contains(Reg))
37 assert(SystemZ::GR32BitRegClass.contains(Reg) && "Invalid GRX32");
45 : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
64 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
65 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
97 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
134 SystemZ::LR, 32, MI.getOperand(1).isKill())
[all...] |
| SystemZShortenInst.cpp | 24 #define DEBUG_TYPE "systemz-shorten-inst"
33 return "SystemZ Instruction Shortening";
82 (SystemZ::GRH32BitRegClass.contains(Reg) ? SystemZ::subreg_h32
83 : SystemZ::subreg_l32);
85 (thisSubRegIdx == SystemZ::subreg_l32 ? SystemZ::subreg_h32
86 : SystemZ::subreg_l32);
88 TRI->getMatchingSuperReg(Reg, thisSubRegIdx, &SystemZ::GR64BitRegClass);
94 if (SystemZ::isImmLL(Imm))
[all...] |
| SystemZAsmPrinter.cpp | 1 //===-- SystemZAsmPrinter.cpp - SystemZ LLVM assembly printer -------------===//
10 // Streams SystemZ assembly language and associated data, in the form of
108 case SystemZ::Return:
109 LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R14D);
112 case SystemZ::CondReturn:
113 LoweredMI = MCInstBuilder(SystemZ::BCR)
116 .addReg(SystemZ::R14D);
119 case SystemZ::CRBReturn:
120 LoweredMI = MCInstBuilder(SystemZ::CRB
[all...] |
| SystemZLongBranch.cpp | 1 //===-- SystemZLongBranch.cpp - Branch lengthening for SystemZ ------------===//
35 // On SystemZ, long branches are only needed for functions bigger than 64k,
68 #define DEBUG_TYPE "systemz-long-branch"
137 return "SystemZ Long Branch";
218 case SystemZ::J:
222 case SystemZ::BRC:
226 case SystemZ::BRCT:
227 case SystemZ::BRCTG:
231 case SystemZ::CRJ:
232 case SystemZ::CLRJ
[all...] |
| SystemZFrameLowering.cpp | 1 //===-- SystemZFrameLowering.cpp - Frame lowering for SystemZ -------------===//
28 { SystemZ::R2D, 0x10 },
29 { SystemZ::R3D, 0x18 },
30 { SystemZ::R4D, 0x20 },
31 { SystemZ::R5D, 0x28 },
32 { SystemZ::R6D, 0x30 },
33 { SystemZ::R7D, 0x38 },
34 { SystemZ::R8D, 0x40 },
35 { SystemZ::R9D, 0x48 },
36 { SystemZ::R10D, 0x50 }
[all...] |
| SystemZTDC.cpp | 47 #include "SystemZ.h"
115 INITIALIZE_PASS(SystemZTDCPass, "systemz-tdc",
116 "SystemZ Test Data Class optimization", false, false)
161 SystemZ::TDCMASK_ZERO, // eq
162 SystemZ::TDCMASK_POSITIVE, // gt
163 SystemZ::TDCMASK_NEGATIVE, // lt
164 SystemZ::TDCMASK_NAN, // un
167 SystemZ::TDCMASK_INFINITY_PLUS, // eq
169 (SystemZ::TDCMASK_ZERO |
170 SystemZ::TDCMASK_NEGATIVE
[all...] |
| SystemZRegisterInfo.cpp | 1 //===-- SystemZRegisterInfo.cpp - SystemZ register information ------------===//
23 : SystemZGenRegisterInfo(SystemZ::R14D) {}
51 Reserved.set(SystemZ::R11D);
52 Reserved.set(SystemZ::R11L);
53 Reserved.set(SystemZ::R11H);
54 Reserved.set(SystemZ::R10Q);
58 Reserved.set(SystemZ::R15D);
59 Reserved.set(SystemZ::R15L);
60 Reserved.set(SystemZ::R15H);
61 Reserved.set(SystemZ::R14Q)
[all...] |
| SystemZElimCompare.cpp | 28 #define DEBUG_TYPE "systemz-elim-compare"
62 return "SystemZ Comparison Elimination";
98 if ((*SI)->isLiveIn(SystemZ::CC))
110 case SystemZ::LR:
111 case SystemZ::LGR:
112 case SystemZ::LGFR:
113 case SystemZ::LTR:
114 case SystemZ::LTGR:
115 case SystemZ::LTGFR:
116 case SystemZ::LER
[all...] |
| SystemZISelLowering.cpp | 1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
28 #define DEBUG_TYPE "systemz-lower"
91 addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass);
93 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
94 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
96 addRegisterClass(MVT::f32, &SystemZ::VR32BitRegClass);
97 addRegisterClass(MVT::f64, &SystemZ::VR64BitRegClass);
99 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
100 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass);
102 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass)
[all...] |
| SystemZRegisterInfo.h | 1 //===-- SystemZRegisterInfo.h - SystemZ register information ----*- C++ -*-===//
13 #include "SystemZ.h"
21 namespace SystemZ {
30 } // end namespace SystemZ
42 return &SystemZ::ADDR64BitRegClass;
|
| SystemZLDCleanup.cpp | 37 return "SystemZ Local Dynamic TLS Access Clean-up";
96 case SystemZ::TLS_LDCALL:
121 TII->get(TargetOpcode::COPY), SystemZ::R2D)
136 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&SystemZ::GR64BitRegClass);
142 .addReg(SystemZ::R2D);
|
| SystemZISelDAGToDAG.cpp | 1 //===-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ --===//
10 // This file defines an instruction selector for the SystemZ target.
22 #define DEBUG_TYPE "systemz-isel"
343 return "SystemZ DAG->DAG Pattern Instruction Selection";
750 if (RxSBG.Opcode == SystemZ::RNSBG)
760 if (RxSBG.Opcode == SystemZ::RNSBG)
784 if (RxSBG.Opcode != SystemZ::RNSBG)
826 if (RxSBG.Opcode != SystemZ::RNSBG) {
858 if (RxSBG.Opcode == SystemZ::RNSBG) {
885 if (RxSBG.Opcode == SystemZ::RNSBG || Opcode == ISD::SRA)
[all...] |
| SystemZCallingConv.h | 1 //===-- SystemZCallingConv.h - Calling conventions for SystemZ --*- C++ -*-===//
18 namespace SystemZ {
24 } // end namespace SystemZ
111 unsigned Reg = State.AllocateReg(SystemZ::ArgGPRs);
|
| /external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| SystemZMCTargetDesc.cpp | 1 //===-- SystemZMCTargetDesc.cpp - SystemZ target descriptions -------------===//
31 SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L,
32 SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L,
33 SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L
[all...] |
| SystemZMCFixups.h | 1 //===-- SystemZMCFixups.h - SystemZ-specific fixup entries ------*- C++ -*-===//
16 namespace SystemZ {
27 } // end namespace SystemZ
|
| SystemZMCObjectWriter.cpp | 1 //===-- SystemZMCObjectWriter.cpp - SystemZ ELF writer --------------------===//
56 case SystemZ::FK_390_PC16DBL: return ELF::R_390_PC16DBL;
57 case SystemZ::FK_390_PC32DBL: return ELF::R_390_PC32DBL;
85 case SystemZ::FK_390_TLS_CALL: return ELF::R_390_TLS_LDCALL;
95 case SystemZ::FK_390_TLS_CALL: return ELF::R_390_TLS_GDCALL;
103 case SystemZ::FK_390_PC16DBL: return ELF::R_390_PLT16DBL;
104 case SystemZ::FK_390_PC32DBL: return ELF::R_390_PLT32DBL;
126 if (IsPCRel && Kind == SystemZ::FK_390_PC32DBL)
143 if (IsPCRel && Kind == SystemZ::FK_390_PC32DBL)
|
| SystemZMCAsmBackend.cpp | 1 //===-- SystemZMCAsmBackend.cpp - SystemZ assembler backend ---------------===//
28 case SystemZ::FK_390_PC16DBL:
29 case SystemZ::FK_390_PC32DBL:
32 case SystemZ::FK_390_TLS_CALL:
48 return SystemZ::NumTargetFixupKinds;
63 llvm_unreachable("SystemZ does do not have assembler relaxation");
74 const static MCFixupKindInfo Infos[SystemZ::NumTargetFixupKinds] = {
|
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| SystemZRegisterInfo.cpp | 1 //===- SystemZRegisterInfo.cpp - SystemZ Register Information -------*- C++ -*-===//
10 // This file contains the SystemZ implementation of the TargetRegisterInfo class.
14 #include "SystemZ.h"
42 SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D,
43 SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D
[all...] |
| SystemZInstrInfo.cpp | 1 //===- SystemZInstrInfo.cpp - SystemZ Instruction Information --------------===//
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
14 #include "SystemZ.h"
33 : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN),
52 if (RC == &SystemZ::GR32RegClass ||
53 RC == &SystemZ::ADDR32RegClass)
54 Opc = SystemZ::MOV32mr;
55 else if (RC == &SystemZ::GR64RegClass ||
56 RC == &SystemZ::ADDR64RegClass)
[all...] |
| SystemZFrameLowering.cpp | 1 //=====- SystemZFrameLowering.cpp - SystemZ Frame Information ------*- C++ -*-====//
10 // This file contains the SystemZ implementation of TargetFrameLowering class.
34 { SystemZ::R2D, 0x10 },
35 { SystemZ::R3D, 0x18 },
36 { SystemZ::R4D, 0x20 },
37 { SystemZ::R5D, 0x28 },
38 { SystemZ::R6D, 0x30 },
39 { SystemZ::R7D, 0x38 },
40 { SystemZ::R8D, 0x40 },
41 { SystemZ::R9D, 0x48 }
[all...] |
| Makefile | 1 ##===- lib/Target/SystemZ/Makefile ---------------------------*- Makefile -*-===##
12 TARGET = SystemZ
|
| SystemZISelDAGToDAG.cpp | 1 //==-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ ---===//
10 // This file defines an instruction selector for the SystemZ target.
14 #include "SystemZ.h"
77 /// SystemZDAGToDAGISel - SystemZ specific code to select SystemZ machine
98 return "SystemZ DAG->DAG Pattern Instruction Selection";
148 /// SystemZ-specific DAG, ready for instruction scheduling.
613 Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m;
618 Opc = SystemZ::SDIVREM64r; MOpc = SystemZ::SDIVREM64m
[all...] |
| SystemZISelLowering.cpp | 1 //===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation -----==//
14 #define DEBUG_TYPE "systemz-lower"
17 #include "SystemZ.h"
49 addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
50 addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
51 addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass);
52 addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass);
55 addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass);
56 addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass);
75 setStackPointerRegisterToSaveRestore(SystemZ::R15D)
[all...] |
| /external/swiftshader/third_party/LLVM/test/CodeGen/SystemZ/ |
| dg.exp | 3 if { [llvm_supports_target SystemZ] } {
|
