| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| tgsi_util.c | 255 read_mask = TGSI_WRITEMASK_X;
259 read_mask = write_mask & TGSI_WRITEMASK_XY ? TGSI_WRITEMASK_X : 0;
264 read_mask = write_mask & TGSI_WRITEMASK_XYZ ? TGSI_WRITEMASK_X : 0;
268 read_mask = src_idx == 2 ? TGSI_WRITEMASK_X : TGSI_WRITEMASK_XY;
296 read_mask = TGSI_WRITEMASK_X;
|
| tgsi_lowering.c | 249 if (dst->Register.WriteMask & TGSI_WRITEMASK_X) {
254 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_X);
346 if (aliases(dst, TGSI_WRITEMASK_X, src, TGSI_WRITEMASK_X)) {
347 create_mov(tctx, &ctx->tmp[A].dst, src, TGSI_WRITEMASK_X, 0);
351 if (dst->Register.WriteMask & TGSI_WRITEMASK_X) {
356 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_X);
510 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_X);
519 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_X);
686 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_X);
[all...] |
| tgsi_aa_point.c | 158 TGSI_FILE_TEMPORARY, tmp0, TGSI_WRITEMASK_X,
164 TGSI_FILE_TEMPORARY, tmp0, TGSI_WRITEMASK_X,
|
| tgsi_point_sprite.c | 296 TGSI_FILE_TEMPORARY, ts->point_scale_tmp, TGSI_WRITEMASK_X,
322 TGSI_WRITEMASK_X,
330 TGSI_WRITEMASK_X,
443 TGSI_FILE_TEMPORARY, ts->point_size_tmp, TGSI_WRITEMASK_X,
449 TGSI_FILE_TEMPORARY, ts->point_size_tmp, TGSI_WRITEMASK_X,
|
| tgsi_transform.h | 362 case TGSI_WRITEMASK_X:
411 case TGSI_WRITEMASK_X:
469 case TGSI_WRITEMASK_X:
|
| /external/mesa3d/src/gallium/auxiliary/vl/ |
| vl_deint_filter.c | 176 ureg_ADD(shader, ureg_writemask(t_diff, TGSI_WRITEMASK_X), ureg_src(t_a), ureg_negate(ureg_src(t_b)));
186 ureg_ADD(shader, ureg_writemask(t_diff, TGSI_WRITEMASK_X), ureg_src(t_a), ureg_negate(ureg_src(t_b)));
194 ureg_MAX(shader, ureg_writemask(t_diff, TGSI_WRITEMASK_X), ureg_abs(ureg_src(t_diff)),
214 ureg_ADD(shader, ureg_writemask(t_diff, TGSI_WRITEMASK_X), ureg_src(t_diff),
216 ureg_MUL(shader, ureg_saturate(ureg_writemask(t_diff, TGSI_WRITEMASK_X)),
218 ureg_LRP(shader, ureg_writemask(t_tex, TGSI_WRITEMASK_X), ureg_src(t_diff),
|
| vl_zscan.c | 153 ureg_ADD(shader, ureg_writemask(tmp, TGSI_WRITEMASK_X), ureg_scalar(ureg_src(tmp), TGSI_SWIZZLE_Y),
157 ureg_MAD(shader, ureg_writemask(o_vtex[i], TGSI_WRITEMASK_X), vrect,
212 ureg_TEX(shader, ureg_writemask(tmp[i], TGSI_WRITEMASK_X), TGSI_TEXTURE_2D, vtex[i], samp_scan);
218 ureg_TEX(shader, ureg_writemask(tmp[0], TGSI_WRITEMASK_X << i), TGSI_TEXTURE_2D, ureg_src(tmp[i]), samp_src);
219 ureg_TEX(shader, ureg_writemask(quant, TGSI_WRITEMASK_X << i), TGSI_TEXTURE_3D, vtex[i], samp_quant);
|
| vl_idct.c | 76 unsigned wm_start = (right_side == transposed) ? TGSI_WRITEMASK_X : TGSI_WRITEMASK_Y;
79 unsigned wm_tc = (right_side == transposed) ? TGSI_WRITEMASK_Y : TGSI_WRITEMASK_X;
100 unsigned wm_start = (right_side == transposed) ? TGSI_WRITEMASK_X : TGSI_WRITEMASK_Y;
101 unsigned wm_tc = (right_side == transposed) ? TGSI_WRITEMASK_Y : TGSI_WRITEMASK_X;
133 ureg_DP4(shader, ureg_writemask(tmp, TGSI_WRITEMASK_X), ureg_src(l[0]), ureg_src(r[0]));
374 matrix_mul(shader, ureg_writemask(fragment[i], TGSI_WRITEMASK_X << j), l[j], r);
|
| vl_compositor.c | 102 ureg_MUL(shader, ureg_writemask(tmp, TGSI_WRITEMASK_X),
107 ureg_MOV(shader, ureg_writemask(o_vtop, TGSI_WRITEMASK_X), vtex);
115 ureg_MOV(shader, ureg_writemask(o_vbottom, TGSI_WRITEMASK_X), vtex);
153 ureg_MOV(shader, ureg_writemask(t_tc[i], TGSI_WRITEMASK_X), i_tc[i]);
177 ureg_TEX(shader, ureg_writemask(t_texel[i], TGSI_WRITEMASK_X << j),
220 ureg_DP4(shader, ureg_writemask(fragment, TGSI_WRITEMASK_X << i), csc[i],
262 ureg_TEX(shader, ureg_writemask(texel, TGSI_WRITEMASK_X << i), TGSI_TEXTURE_2D_ARRAY, tc, sampler[i]);
311 ureg_MOV(shader, ureg_writemask(fragment, TGSI_WRITEMASK_X), ureg_src(texel));
361 ureg_DP4(shader, ureg_writemask(fragment, TGSI_WRITEMASK_X << i), csc[i], ureg_src(texel));
[all...] |
| /external/mesa3d/src/mesa/state_tracker/ |
| st_tgsi_lower_yuv.c | 273 reg_dst(&inst.Dst[0], dst, TGSI_WRITEMASK_X);
312 reg_dst(&inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_X);
347 reg_dst(&inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_X);
356 reg_dst(&inst.Dst[0], &ctx->tmp[B].dst, TGSI_WRITEMASK_X);
370 reg_dst(&inst.Dst[0], &ctx->tmp[B].dst, TGSI_WRITEMASK_X);
|
| st_pbo.c | 378 ureg_F2I(ureg, ureg_writemask(out_layer, TGSI_WRITEMASK_X),
478 ureg_UMAD(ureg, ureg_writemask(temp0, TGSI_WRITEMASK_X),
485 ureg_UMAD(ureg, ureg_writemask(temp0, TGSI_WRITEMASK_X),
|
| st_mesa_to_tgsi.c | 906 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
945 ureg_U2F( t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X), t->systemValues[i]);
[all...] |
| /external/mesa3d/src/gallium/state_trackers/nine/ |
| nine_shader.c | 697 return ureg_writemask(tx_scratch(tx), TGSI_WRITEMASK_X);
[all...] |
| nine_ff.c | 324 struct ureg_dst tmp_x = ureg_writemask(tmp, TGSI_WRITEMASK_X);
425 oFog = ureg_writemask(oFog, TGSI_WRITEMASK_X);
430 TGSI_WRITEMASK_X, 0, 1);
431 oPsz = ureg_writemask(oPsz, TGSI_WRITEMASK_X);
588 struct ureg_dst tmp_x = ureg_writemask(tmp, TGSI_WRITEMASK_X);
635 tmp_x = ureg_writemask(tmp, TGSI_WRITEMASK_X);
683 ureg_DP3(ureg, ureg_writemask(tmp2, TGSI_WRITEMASK_X), ureg_src(tmp2), ureg_src(tmp2));
684 ureg_RSQ(ureg, ureg_writemask(tmp2, TGSI_WRITEMASK_X), ureg_src(tmp2));
685 ureg_MUL(ureg, ureg_writemask(tmp2, TGSI_WRITEMASK_X), ureg_src(tmp2), ureg_imm1f(ureg, 0.5f));
778 struct ureg_dst tmp_x = ureg_writemask(tmp, TGSI_WRITEMASK_X);
[all...] |
| /external/mesa3d/src/gallium/auxiliary/draw/ |
| draw_pipe_aapoint.c | 220 TGSI_FILE_TEMPORARY, tmp0, TGSI_WRITEMASK_X,
227 TGSI_FILE_TEMPORARY, tmp0, TGSI_WRITEMASK_X,
232 TGSI_FILE_TEMPORARY, tmp0, TGSI_WRITEMASK_X,
|
| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| lp_bld_tgsi_info.c | 121 readmask = TGSI_WRITEMASK_X;
220 readmask = TGSI_WRITEMASK_X;
|
| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_fpc_optimize.c | 157 mask |= TGSI_WRITEMASK_X;
165 if ( write_mask & TGSI_WRITEMASK_X && r->Register.SwizzleX != TGSI_SWIZZLE_X)
199 if ( write_mask & TGSI_WRITEMASK_X )
460 if (dst_reg2->Register.WriteMask & TGSI_WRITEMASK_X)
|
| i915_fpc_translate.c | 335 if (writeMask & TGSI_WRITEMASK_X)
846 if (writemask & TGSI_WRITEMASK_X)
865 if (writemask & TGSI_WRITEMASK_X) {
[all...] |
| /external/mesa3d/src/gallium/drivers/svga/ |
| svga_tgsi_vgpu10.c | 938 STATIC_ASSERT(TGSI_WRITEMASK_X == VGPU10_OPERAND_4_COMPONENT_MASK_X);
[all...] |
| svga_tgsi_insn.c | [all...] |
| /external/mesa3d/src/gallium/include/pipe/ |
| p_shader_tokens.h | 83 #define TGSI_WRITEMASK_X 0x01
132 unsigned UsageMask : 4; /**< bitmask of TGSI_WRITEMASK_x flags */
|
| /external/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
| fd2_compiler.c | 348 swiz[0] = (dst->WriteMask & TGSI_WRITEMASK_X) ? 'x' : '_';
710 case TGSI_WRITEMASK_X:
939 tmp_dst.WriteMask = TGSI_WRITEMASK_X;
|
| /external/mesa3d/src/gallium/drivers/llvmpipe/ |
| lp_setup_point.c | 181 if (usage_mask & TGSI_WRITEMASK_X) {
|
| /external/mesa3d/src/gallium/state_trackers/xa/ |
| xa_tgsi.c | 171 ureg_MOV(ureg, ureg_writemask(temp4, TGSI_WRITEMASK_X), ureg_src(temp1));
222 ureg_MOV(ureg, ureg_writemask(temp5, TGSI_WRITEMASK_X), ureg_src(temp1));
|
| /external/mesa3d/src/gallium/drivers/nouveau/nv50/ |
| nv50_surface.c | 931 ureg_TEX(ureg, ureg_writemask(data, TGSI_WRITEMASK_X),
938 TGSI_WRITEMASK_XYZW : TGSI_WRITEMASK_X;
949 struct ureg_dst zdst = ureg_writemask(data, TGSI_WRITEMASK_X);
969 outs = ureg_writemask(out, TGSI_WRITEMASK_X);
993 mask = TGSI_WRITEMASK_X;
[all...] |
