| /toolchain/binutils/binutils-2.27/opcodes/ |
| tilegx-opc.c | 29 #define TREG_ZERO 63
47 { "bpt", TILEGX_OPC_BPT, 0x2, 0, TREG_ZERO, 0,
66 { "info", TILEGX_OPC_INFO, 0xf, 1, TREG_ZERO, 1,
85 { "infol", TILEGX_OPC_INFOL, 0x3, 1, TREG_ZERO, 1,
104 { "ld4s_tls", TILEGX_OPC_LD4S_TLS, 0x2, 3, TREG_ZERO, 1,
123 { "ld_tls", TILEGX_OPC_LD_TLS, 0x2, 3, TREG_ZERO, 1,
142 { "move", TILEGX_OPC_MOVE, 0xf, 2, TREG_ZERO, 1,
161 { "movei", TILEGX_OPC_MOVEI, 0xf, 2, TREG_ZERO, 1,
180 { "moveli", TILEGX_OPC_MOVELI, 0x3, 2, TREG_ZERO, 1,
199 { "prefetch", TILEGX_OPC_PREFETCH, 0x12, 1, TREG_ZERO, 1
[all...] |
| tilepro-opc.c | 29 #define TREG_ZERO 63
47 { "bpt", TILEPRO_OPC_BPT, 0x2, 0, TREG_ZERO, 0,
66 { "info", TILEPRO_OPC_INFO, 0xf, 1, TREG_ZERO, 1,
85 { "infol", TILEPRO_OPC_INFOL, 0x3, 1, TREG_ZERO, 1,
104 { "j", TILEPRO_OPC_J, 0x2, 1, TREG_ZERO, 1,
142 { "lw_tls", TILEPRO_OPC_LW_TLS, 0x2, 3, TREG_ZERO, 1,
180 { "move", TILEPRO_OPC_MOVE, 0xf, 2, TREG_ZERO, 1,
218 { "movei", TILEPRO_OPC_MOVEI, 0xf, 2, TREG_ZERO, 1,
256 { "moveli", TILEPRO_OPC_MOVELI, 0x3, 2, TREG_ZERO, 1,
313 { "prefetch", TILEPRO_OPC_PREFETCH, 0x12, 1, TREG_ZERO, 1
[all...] |
| tilepro-dis.c | 31 #define TREG_ZERO 63
181 TREG_ZERO,
|
| /external/pcre/dist2/src/sljit/ |
| sljitNativeTILEGX-encoder.c | 39 #define TREG_ZERO 63
640 /* Which register does this write implicitly, or TREG_ZERO if none? */
[all...] |
| /toolchain/binutils/binutils-2.27/gas/config/ |
| tc-tilegx.c | 41 #define TREG_ZERO 63
831 regs &= ~(((BFD_HOST_U_64_BIT)1) << TREG_ZERO);
[all...] |
| tc-tilepro.c | 41 #define TREG_ZERO 63
722 regs &= ~(((BFD_HOST_U_64_BIT)1) << TREG_ZERO);
[all...] |
