HomeSort by relevance Sort by last modified time
    Searched refs:TReg (Results 1 - 4 of 4) sorted by null

  /external/llvm/lib/CodeGen/
EarlyIfConversion.cpp 112 unsigned TReg, FReg;
113 // Latencies from Cond+Branch, TReg, and FReg to DstReg.
117 : PHI(phi), TReg(0), FReg(0), CondCycles(0), TCycles(0), FCycles(0) {}
415 PI.TReg = PI.PHI->getOperand(i).getReg();
419 assert(TargetRegisterInfo::isVirtualRegister(PI.TReg) && "Bad PHI");
423 if (!TII->canInsertSelect(*Head, Cond, PI.TReg, PI.FReg,
464 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg);
485 if (PI.TReg == PI.FReg) {
488 DstReg = PI.TReg;
493 DstReg, Cond, PI.TReg, PI.FReg)
    [all...]
  /external/swiftshader/third_party/subzero/src/
IceTargetLoweringMIPS32.cpp     [all...]
  /external/llvm/lib/Target/Mips/AsmParser/
MipsAsmParser.cpp     [all...]
  /external/llvm/lib/Target/ARM/
ARMAsmPrinter.cpp     [all...]

Completed in 142 milliseconds