/external/python/cpython3/Modules/_decimal/libmpdec/ |
constants.c | 38 18446744069414584321ULL, 18446744056529682433ULL, 18446742974197923841ULL 40 const mpd_uint_t mpd_roots[3] = {7ULL, 10ULL, 19ULL}; 43 const mpd_uint_t INV_P1_MOD_P2 = 18446744055098026669ULL; 44 const mpd_uint_t INV_P1P2_MOD_P3 = 287064143708160ULL; 45 const mpd_uint_t LH_P1P2 = 18446744052234715137ULL; /* (P1*P2) % 2^64 */ 46 const mpd_uint_t UH_P1P2 = 18446744052234715141ULL; /* (P1*P2) / 2^64 * [all...] |
/external/capstone/arch/Sparc/ |
SparcGenSubtargetInfo.inc | 17 Sparc_FeatureHardQuad = 1ULL << 0, 18 Sparc_FeatureV8Deprecated = 1ULL << 1, 19 Sparc_FeatureV9 = 1ULL << 2, 20 Sparc_FeatureVIS = 1ULL << 3, 21 Sparc_FeatureVIS2 = 1ULL << 4, 22 Sparc_FeatureVIS3 = 1ULL << 5, 23 Sparc_UsePopc = 1ULL << 6
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/external/capstone/arch/PowerPC/ |
PPCGenSubtargetInfo.inc | 16 #define PPC_DeprecatedDST (1ULL << 0) 17 #define PPC_DeprecatedMFTB (1ULL << 1) 18 #define PPC_Directive32 (1ULL << 2) 19 #define PPC_Directive64 (1ULL << 3) 20 #define PPC_Directive440 (1ULL << 4) 21 #define PPC_Directive601 (1ULL << 5) 22 #define PPC_Directive602 (1ULL << 6) 23 #define PPC_Directive603 (1ULL << 7) 24 #define PPC_Directive604 (1ULL << 8) 25 #define PPC_Directive620 (1ULL << 9 [all...] |
/external/capstone/arch/AArch64/ |
AArch64GenSubtargetInfo.inc | 17 AArch64_FeatureCRC = 1ULL << 0, 18 AArch64_FeatureCrypto = 1ULL << 1, 19 AArch64_FeatureFPARMv8 = 1ULL << 2, 20 AArch64_FeatureNEON = 1ULL << 3, 21 AArch64_FeatureZCRegMove = 1ULL << 4, 22 AArch64_FeatureZCZeroing = 1ULL << 5, 23 AArch64_ProcA53 = 1ULL << 6, 24 AArch64_ProcA57 = 1ULL << 7, 25 AArch64_ProcCyclone = 1ULL << 8
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/external/capstone/arch/Mips/ |
MipsGenSubtargetInfo.inc | 16 #define Mips_FeatureCnMips (1ULL << 0) 17 #define Mips_FeatureDSP (1ULL << 1) 18 #define Mips_FeatureDSPR2 (1ULL << 2) 19 #define Mips_FeatureEABI (1ULL << 3) 20 #define Mips_FeatureFP64Bit (1ULL << 4) 21 #define Mips_FeatureFPXX (1ULL << 5) 22 #define Mips_FeatureGP64Bit (1ULL << 6) 23 #define Mips_FeatureMSA (1ULL << 7) 24 #define Mips_FeatureMicroMips (1ULL << 8) 25 #define Mips_FeatureMips1 (1ULL << 9 [all...] |
/external/clang/test/CodeGen/ |
builtins-ppc-p7-disabled.c | 13 unsigned long long d = __builtin_divde(33ULL, 11ULL); 14 unsigned long long e = __builtin_divdeu(33ULL, 11ULL); 15 unsigned long long f = __builtin_bpermd(33ULL, 11ULL);
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/external/capstone/arch/SystemZ/ |
SystemZGenSubtargetInfo.inc | 17 SystemZ_FeatureDistinctOps = 1ULL << 0, 18 SystemZ_FeatureFPExtension = 1ULL << 1, 19 SystemZ_FeatureFastSerialization = 1ULL << 2, 20 SystemZ_FeatureHighWord = 1ULL << 3, 21 SystemZ_FeatureInterlockedAccess1 = 1ULL << 4, 22 SystemZ_FeatureLoadStoreOnCond = 1ULL << 5
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/toolchain/binutils/binutils-2.27/opcodes/ |
tilegx-opc.c | 51 0ULL, 53 0ULL, 54 0ULL, 55 0ULL 58 -1ULL, 60 -1ULL, 61 -1ULL, 62 -1ULL 74 0ULL 81 -1ULL [all...] |
tilepro-opc.c | 51 0ULL, 53 0ULL, 54 0ULL, 55 0ULL 58 -1ULL, 60 -1ULL, 61 -1ULL, 62 -1ULL 74 0ULL 81 -1ULL [all...] |
/external/strace/xlat/ |
cap_mask0.h | 11 XLAT_PAIR(1ULL<<CAP_CHOWN, "1<<CAP_CHOWN"), 12 XLAT_PAIR(1ULL<<CAP_DAC_OVERRIDE, "1<<CAP_DAC_OVERRIDE"), 13 XLAT_PAIR(1ULL<<CAP_DAC_READ_SEARCH, "1<<CAP_DAC_READ_SEARCH"), 14 XLAT_PAIR(1ULL<<CAP_FOWNER, "1<<CAP_FOWNER"), 15 XLAT_PAIR(1ULL<<CAP_FSETID, "1<<CAP_FSETID"), 16 XLAT_PAIR(1ULL<<CAP_KILL, "1<<CAP_KILL"), 17 XLAT_PAIR(1ULL<<CAP_SETGID, "1<<CAP_SETGID"), 18 XLAT_PAIR(1ULL<<CAP_SETUID, "1<<CAP_SETUID"), 19 XLAT_PAIR(1ULL<<CAP_SETPCAP, "1<<CAP_SETPCAP"), 20 XLAT_PAIR(1ULL<<CAP_LINUX_IMMUTABLE, "1<<CAP_LINUX_IMMUTABLE") [all...] |
cap_mask1.h | 11 XLAT_PAIR(1ULL<<CAP_MAC_OVERRIDE, "1<<CAP_MAC_OVERRIDE"), 12 XLAT_PAIR(1ULL<<CAP_MAC_ADMIN, "1<<CAP_MAC_ADMIN"), 13 XLAT_PAIR(1ULL<<CAP_SYSLOG, "1<<CAP_SYSLOG"), 14 XLAT_PAIR(1ULL<<CAP_WAKE_ALARM, "1<<CAP_WAKE_ALARM"), 15 XLAT_PAIR(1ULL<<CAP_BLOCK_SUSPEND, "1<<CAP_BLOCK_SUSPEND"), 16 XLAT_PAIR(1ULL<<CAP_AUDIT_READ, "1<<CAP_AUDIT_READ"),
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tcp_state_flags.h | 8 XLAT_PAIR(1ULL<<TCP_ESTABLISHED, "1<<TCP_ESTABLISHED"), 11 XLAT_PAIR(1ULL<<TCP_SYN_SENT, "1<<TCP_SYN_SENT"), 14 XLAT_PAIR(1ULL<<TCP_SYN_RECV, "1<<TCP_SYN_RECV"), 17 XLAT_PAIR(1ULL<<TCP_FIN_WAIT1, "1<<TCP_FIN_WAIT1"), 20 XLAT_PAIR(1ULL<<TCP_FIN_WAIT2, "1<<TCP_FIN_WAIT2"), 23 XLAT_PAIR(1ULL<<TCP_TIME_WAIT, "1<<TCP_TIME_WAIT"), 26 XLAT_PAIR(1ULL<<TCP_CLOSE, "1<<TCP_CLOSE"), 29 XLAT_PAIR(1ULL<<TCP_CLOSE_WAIT, "1<<TCP_CLOSE_WAIT"), 32 XLAT_PAIR(1ULL<<TCP_LAST_ACK, "1<<TCP_LAST_ACK"), 35 XLAT_PAIR(1ULL<<TCP_LISTEN, "1<<TCP_LISTEN") [all...] |
btrfs_qgroup_limit_flags.h | 3 # define BTRFS_QGROUP_LIMIT_MAX_RFER (1ULL << 0) 6 # define BTRFS_QGROUP_LIMIT_MAX_EXCL (1ULL << 1) 9 # define BTRFS_QGROUP_LIMIT_RSV_RFER (1ULL << 2) 12 # define BTRFS_QGROUP_LIMIT_RSV_EXCL (1ULL << 3) 15 # define BTRFS_QGROUP_LIMIT_RFER_CMPR (1ULL << 4) 18 # define BTRFS_QGROUP_LIMIT_EXCL_CMPR (1ULL << 5)
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/external/capstone/arch/ARM/ |
ARMGenSubtargetInfo.inc | 16 #define ARM_FeatureAAPCS (1ULL << 0) 17 #define ARM_FeatureAClass (1ULL << 1) 18 #define ARM_FeatureAPCS (1ULL << 2) 19 #define ARM_FeatureAvoidMOVsShOp (1ULL << 3) 20 #define ARM_FeatureAvoidPartialCPSR (1ULL << 4) 21 #define ARM_FeatureCRC (1ULL << 5) 22 #define ARM_FeatureCrypto (1ULL << 6) 23 #define ARM_FeatureD16 (1ULL << 7) 24 #define ARM_FeatureDB (1ULL << 8) 25 #define ARM_FeatureDSPThumb2 (1ULL << 9 [all...] |
/external/pcre/dist2/src/sljit/ |
sljitNativeTILEGX-encoder.c | [all...] |
/device/google/wahoo/ |
android_filesystem_config.h | 34 { 00755, AID_SYSTEM, AID_SYSTEM, (1ULL << CAP_NET_BIND_SERVICE), "vendor/bin/pm-service" }, 35 { 00755, AID_SYSTEM, AID_SYSTEM, (1ULL << CAP_NET_BIND_SERVICE), "vendor/bin/cnss-daemon"}, 36 { 00755, AID_SYSTEM, AID_SYSTEM, (1ULL << CAP_NET_BIND_SERVICE), "vendor/bin/imsdatadaemon" }, 37 { 00755, AID_SYSTEM, AID_SYSTEM, (1ULL << CAP_NET_BIND_SERVICE) 38 | (1ULL << CAP_BLOCK_SUSPEND), "vendor/bin/cnd" }, 39 { 00755, AID_SYSTEM, AID_RADIO, (1ULL << CAP_NET_BIND_SERVICE), "vendor/bin/ims_rtp_daemon" }, 40 { 00755, AID_SYSTEM, AID_SYSTEM, (1ULL << CAP_SYS_NICE) | (1ULL << CAP_BLOCK_SUSPEND), "vendor/bin/wcnss_filter" },
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/external/fio/ |
optgroup.h | 19 FIO_OPT_C_GENERAL = (1ULL << __FIO_OPT_C_GENERAL), 20 FIO_OPT_C_IO = (1ULL << __FIO_OPT_C_IO), 21 FIO_OPT_C_FILE = (1ULL << __FIO_OPT_C_FILE), 22 FIO_OPT_C_STAT = (1ULL << __FIO_OPT_C_STAT), 23 FIO_OPT_C_LOG = (1ULL << __FIO_OPT_C_LOG), 24 FIO_OPT_C_PROFILE = (1ULL << __FIO_OPT_C_PROFILE), 25 FIO_OPT_C_ENGINE = (1ULL << __FIO_OPT_C_ENGINE), 26 FIO_OPT_C_INVALID = (1ULL << __FIO_OPT_C_NR), 64 FIO_OPT_G_RATE = (1ULL << __FIO_OPT_G_RATE), 65 FIO_OPT_G_ZONE = (1ULL << __FIO_OPT_G_ZONE) [all...] |
/external/dhcpcd-6.8.2/ |
if-options.h | 58 #define DHCPCD_ARP (1ULL << 0) 59 #define DHCPCD_RELEASE (1ULL << 1) 60 #define DHCPCD_DOMAIN (1ULL << 2) 61 #define DHCPCD_GATEWAY (1ULL << 3) 62 #define DHCPCD_STATIC (1ULL << 4) 63 #define DHCPCD_DEBUG (1ULL << 5) 64 #define DHCPCD_LASTLEASE (1ULL << 7) 65 #define DHCPCD_INFORM (1ULL << 8) 66 #define DHCPCD_REQUEST (1ULL << 9) 67 #define DHCPCD_IPV4LL (1ULL << 10 [all...] |
/device/google/marlin/marlin/ |
android_filesystem_config.h | 34 { 00755, AID_SYSTEM, AID_SYSTEM, (1ULL << CAP_NET_BIND_SERVICE), "vendor/bin/pm-service" }, 35 { 00755, AID_SYSTEM, AID_SYSTEM, (1ULL << CAP_NET_BIND_SERVICE), "vendor/bin/imsdatadaemon" }, 36 { 00755, AID_SYSTEM, AID_RADIO, (1ULL << CAP_NET_BIND_SERVICE), "vendor/bin/ims_rtp_daemon" }, 37 { 00755, AID_SYSTEM, AID_SYSTEM, (1ULL << CAP_NET_BIND_SERVICE), "vendor/bin/cnss-daemon"}, 38 { 00755, AID_SYSTEM, AID_SYSTEM, (1ULL << CAP_SYS_NICE), "vendor/bin/wcnss_filter"},
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/device/google/marlin/sailfish/ |
android_filesystem_config.h | 34 { 00755, AID_SYSTEM, AID_SYSTEM, (1ULL << CAP_NET_BIND_SERVICE), "vendor/bin/pm-service" }, 35 { 00755, AID_SYSTEM, AID_SYSTEM, (1ULL << CAP_NET_BIND_SERVICE), "vendor/bin/imsdatadaemon" }, 36 { 00755, AID_SYSTEM, AID_RADIO, (1ULL << CAP_NET_BIND_SERVICE), "vendor/bin/ims_rtp_daemon" }, 37 { 00755, AID_SYSTEM, AID_SYSTEM, (1ULL << CAP_NET_BIND_SERVICE), "vendor/bin/cnss-daemon"}, 38 { 00755, AID_SYSTEM, AID_SYSTEM, (1ULL << CAP_SYS_NICE), "vendor/bin/wcnss_filter"},
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/device/linaro/bootloader/arm-trusted-firmware/include/lib/cpus/aarch64/ |
cortex_a72.h | 19 #define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6) 20 #define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38) 21 #define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) 22 #define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) 34 #define CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56) 35 #define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49) 36 #define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44) 37 #define CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32)
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/device/linaro/bootloader/arm-trusted-firmware/include/lib/cpus/aarch32/ |
cortex_a57.h | 28 #define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6) 29 #define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38) 30 #define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) 31 #define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) 34 #define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT) 46 #define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59) 47 #define CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54) 48 #define CORTEX_A57_CPUACTLR_DIS_OVERREAD (ULL(1) << 52) 49 #define CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49) 50 #define CORTEX_A57_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44 [all...] |
/frameworks/native/libs/nativewindow/include/android/ |
hardware_buffer.h | 174 AHARDWAREBUFFER_USAGE_VENDOR_0 = 1ULL << 28, 175 AHARDWAREBUFFER_USAGE_VENDOR_1 = 1ULL << 29, 176 AHARDWAREBUFFER_USAGE_VENDOR_2 = 1ULL << 30, 177 AHARDWAREBUFFER_USAGE_VENDOR_3 = 1ULL << 31, 178 AHARDWAREBUFFER_USAGE_VENDOR_4 = 1ULL << 48, 179 AHARDWAREBUFFER_USAGE_VENDOR_5 = 1ULL << 49, 180 AHARDWAREBUFFER_USAGE_VENDOR_6 = 1ULL << 50, 181 AHARDWAREBUFFER_USAGE_VENDOR_7 = 1ULL << 51, 182 AHARDWAREBUFFER_USAGE_VENDOR_8 = 1ULL << 52, 183 AHARDWAREBUFFER_USAGE_VENDOR_9 = 1ULL << 53 [all...] |
/hardware/libhardware/include/hardware/ |
gralloc1.h | 57 /* 1ULL << 0 */ 58 GRALLOC1_CONSUMER_USAGE_CPU_READ = 1ULL << 1, 59 GRALLOC1_CONSUMER_USAGE_CPU_READ_OFTEN = 1ULL << 2 | 61 /* 1ULL << 3 */ 62 /* 1ULL << 4 */ 63 /* 1ULL << 5 */ 64 /* 1ULL << 6 */ 65 /* 1ULL << 7 */ 66 GRALLOC1_CONSUMER_USAGE_GPU_TEXTURE = 1ULL << 8, 67 /* 1ULL << 9 * [all...] |
/frameworks/native/libs/vr/libdvr/include/dvr/ |
dvr_pose.h | 49 DVR_POSE_FLAG_INVALID = (1ULL << 0), // This pose is invalid. 50 DVR_POSE_FLAG_INITIALIZING = (1ULL << 1), // The pose delivered during 54 (1ULL << 2), // This pose is derived from 3Dof sensors. If 58 (1ULL << 3), // If set the floor height is invalid. 61 DVR_POSE_FLAG_SERVICE_EXCEPTION = (1ULL << 32), 62 DVR_POSE_FLAG_FISHEYE_OVER_EXPOSED = (1ULL << 33), 63 DVR_POSE_FLAG_FISHEYE_UNDER_EXPOSED = (1ULL << 34), 64 DVR_POSE_FLAG_COLOR_OVER_EXPOSED = (1ULL << 35), 65 DVR_POSE_FLAG_COLOR_UNDER_EXPOSED = (1ULL << 36), 66 DVR_POSE_FLAG_TOO_FEW_FEATURES_TRACKED = (1ULL << 37 [all...] |