| /external/vixl/test/aarch32/ |
| test-simulator-cond-rd-operand-rn-a32.cc | 129 M(Uxth)
488 #include "aarch32/traces/simulator-cond-rd-operand-rn-uxth-a32.h"
|
| test-simulator-cond-rd-operand-rn-ror-amount-a32.cc | 121 M(Uxth)
551 #include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-uxth-a32.h"
[all...] |
| test-simulator-cond-rd-operand-rn-ror-amount-t32.cc | 121 M(Uxth)
551 #include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-uxth-t32.h"
[all...] |
| test-simulator-cond-rd-operand-rn-t32.cc | 129 M(Uxth)
488 #include "aarch32/traces/simulator-cond-rd-operand-rn-uxth-t32.h"
|
| test-disasm-a32.cc | [all...] |
| /art/compiler/utils/arm64/ |
| jni_macro_assembler_arm64.cc | 522 ___ Uxth(reg_w(reg.AsWRegister()), reg_w(reg.AsWRegister()));
[all...] |
| /external/v8/src/arm64/ |
| macro-assembler-arm64-inl.h | 1229 void MacroAssembler::Uxth(const Register& rd, const Register& rn) {
1232 uxth(rd, rn);
[all...] |
| macro-assembler-arm64.h | 568 inline void Uxth(const Register& rd, const Register& rn);
[all...] |
| /art/compiler/optimizing/ |
| intrinsics_arm64.cc | [all...] |
| /external/vixl/src/aarch64/ |
| macro-assembler-aarch64.h | [all...] |
| /external/vixl/src/aarch32/ |
| macro-assembler-aarch32.h | [all...] |
| /external/vixl/test/aarch64/ |
| test-assembler-aarch64.cc | 430 __ Mvn(w12, Operand(w2, UXTH, 2));
605 __ Mov(w25, Operand(w13, UXTH, 2));
659 __ Mov(w21, Operand(w11, UXTH, 1));
666 __ Mov(x27, Operand(x12, UXTH, 1));
739 __ Orr(x7, x0, Operand(x1, UXTH, 1));
833 __ Orn(x7, x0, Operand(x1, UXTH, 1));
900 __ And(x7, x0, Operand(x1, UXTH, 1));
1038 __ Bic(x7, x0, Operand(x1, UXTH, 1));
[all...] |
