1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __MEMCTRLV2_H__ 8 #define __MEMCTRLV2_H__ 9 10 #include <tegra_def.h> 11 12 #ifndef __ASSEMBLY__ 13 14 #include <sys/types.h> 15 16 /******************************************************************************* 17 * StreamID to indicate no SMMU translations (requests to be steered on the 18 * SMMU bypass path) 19 ******************************************************************************/ 20 #define MC_STREAM_ID_MAX 0x7F 21 22 /******************************************************************************* 23 * Stream ID Override Config registers 24 ******************************************************************************/ 25 #define MC_STREAMID_OVERRIDE_CFG_PTCR 0x000 26 #define MC_STREAMID_OVERRIDE_CFG_AFIR 0x070 27 #define MC_STREAMID_OVERRIDE_CFG_HDAR 0x0A8 28 #define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR 0x0B0 29 #define MC_STREAMID_OVERRIDE_CFG_NVENCSRD 0x0E0 30 #define MC_STREAMID_OVERRIDE_CFG_SATAR 0x0F8 31 #define MC_STREAMID_OVERRIDE_CFG_MPCORER 0x138 32 #define MC_STREAMID_OVERRIDE_CFG_NVENCSWR 0x158 33 #define MC_STREAMID_OVERRIDE_CFG_AFIW 0x188 34 #define MC_STREAMID_OVERRIDE_CFG_HDAW 0x1A8 35 #define MC_STREAMID_OVERRIDE_CFG_MPCOREW 0x1C8 36 #define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1E8 37 #define MC_STREAMID_OVERRIDE_CFG_ISPRA 0x220 38 #define MC_STREAMID_OVERRIDE_CFG_ISPWA 0x230 39 #define MC_STREAMID_OVERRIDE_CFG_ISPWB 0x238 40 #define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR 0x250 41 #define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW 0x258 42 #define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR 0x260 43 #define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW 0x268 44 #define MC_STREAMID_OVERRIDE_CFG_TSECSRD 0x2A0 45 #define MC_STREAMID_OVERRIDE_CFG_TSECSWR 0x2A8 46 #define MC_STREAMID_OVERRIDE_CFG_GPUSRD 0x2C0 47 #define MC_STREAMID_OVERRIDE_CFG_GPUSWR 0x2C8 48 #define MC_STREAMID_OVERRIDE_CFG_SDMMCRA 0x300 49 #define MC_STREAMID_OVERRIDE_CFG_SDMMCRAA 0x308 50 #define MC_STREAMID_OVERRIDE_CFG_SDMMCR 0x310 51 #define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB 0x318 52 #define MC_STREAMID_OVERRIDE_CFG_SDMMCWA 0x320 53 #define MC_STREAMID_OVERRIDE_CFG_SDMMCWAA 0x328 54 #define MC_STREAMID_OVERRIDE_CFG_SDMMCW 0x330 55 #define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB 0x338 56 #define MC_STREAMID_OVERRIDE_CFG_VICSRD 0x360 57 #define MC_STREAMID_OVERRIDE_CFG_VICSWR 0x368 58 #define MC_STREAMID_OVERRIDE_CFG_VIW 0x390 59 #define MC_STREAMID_OVERRIDE_CFG_NVDECSRD 0x3C0 60 #define MC_STREAMID_OVERRIDE_CFG_NVDECSWR 0x3C8 61 #define MC_STREAMID_OVERRIDE_CFG_APER 0x3D0 62 #define MC_STREAMID_OVERRIDE_CFG_APEW 0x3D8 63 #define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD 0x3F0 64 #define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR 0x3F8 65 #define MC_STREAMID_OVERRIDE_CFG_SESRD 0x400 66 #define MC_STREAMID_OVERRIDE_CFG_SESWR 0x408 67 #define MC_STREAMID_OVERRIDE_CFG_ETRR 0x420 68 #define MC_STREAMID_OVERRIDE_CFG_ETRW 0x428 69 #define MC_STREAMID_OVERRIDE_CFG_TSECSRDB 0x430 70 #define MC_STREAMID_OVERRIDE_CFG_TSECSWRB 0x438 71 #define MC_STREAMID_OVERRIDE_CFG_GPUSRD2 0x440 72 #define MC_STREAMID_OVERRIDE_CFG_GPUSWR2 0x448 73 #define MC_STREAMID_OVERRIDE_CFG_AXISR 0x460 74 #define MC_STREAMID_OVERRIDE_CFG_AXISW 0x468 75 #define MC_STREAMID_OVERRIDE_CFG_EQOSR 0x470 76 #define MC_STREAMID_OVERRIDE_CFG_EQOSW 0x478 77 #define MC_STREAMID_OVERRIDE_CFG_UFSHCR 0x480 78 #define MC_STREAMID_OVERRIDE_CFG_UFSHCW 0x488 79 #define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR 0x490 80 #define MC_STREAMID_OVERRIDE_CFG_BPMPR 0x498 81 #define MC_STREAMID_OVERRIDE_CFG_BPMPW 0x4A0 82 #define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR 0x4A8 83 #define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW 0x4B0 84 #define MC_STREAMID_OVERRIDE_CFG_AONR 0x4B8 85 #define MC_STREAMID_OVERRIDE_CFG_AONW 0x4C0 86 #define MC_STREAMID_OVERRIDE_CFG_AONDMAR 0x4C8 87 #define MC_STREAMID_OVERRIDE_CFG_AONDMAW 0x4D0 88 #define MC_STREAMID_OVERRIDE_CFG_SCER 0x4D8 89 #define MC_STREAMID_OVERRIDE_CFG_SCEW 0x4E0 90 #define MC_STREAMID_OVERRIDE_CFG_SCEDMAR 0x4E8 91 #define MC_STREAMID_OVERRIDE_CFG_SCEDMAW 0x4F0 92 #define MC_STREAMID_OVERRIDE_CFG_APEDMAR 0x4F8 93 #define MC_STREAMID_OVERRIDE_CFG_APEDMAW 0x500 94 #define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1 0x508 95 #define MC_STREAMID_OVERRIDE_CFG_VICSRD1 0x510 96 #define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 0x518 97 98 /******************************************************************************* 99 * Macro to calculate Security cfg register addr from StreamID Override register 100 ******************************************************************************/ 101 #define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) (addr + sizeof(uint32_t)) 102 103 /******************************************************************************* 104 * Memory Controller transaction override config registers 105 ******************************************************************************/ 106 #define MC_TXN_OVERRIDE_CONFIG_HDAR 0x10a8 107 #define MC_TXN_OVERRIDE_CONFIG_BPMPW 0x14a0 108 #define MC_TXN_OVERRIDE_CONFIG_PTCR 0x1000 109 #define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR 0x1490 110 #define MC_TXN_OVERRIDE_CONFIG_EQOSW 0x1478 111 #define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR 0x13f8 112 #define MC_TXN_OVERRIDE_CONFIG_ISPRA 0x1220 113 #define MC_TXN_OVERRIDE_CONFIG_SDMMCWAA 0x1328 114 #define MC_TXN_OVERRIDE_CONFIG_VICSRD 0x1360 115 #define MC_TXN_OVERRIDE_CONFIG_MPCOREW 0x11c8 116 #define MC_TXN_OVERRIDE_CONFIG_GPUSRD 0x12c0 117 #define MC_TXN_OVERRIDE_CONFIG_AXISR 0x1460 118 #define MC_TXN_OVERRIDE_CONFIG_SCEDMAW 0x14f0 119 #define MC_TXN_OVERRIDE_CONFIG_SDMMCW 0x1330 120 #define MC_TXN_OVERRIDE_CONFIG_EQOSR 0x1470 121 #define MC_TXN_OVERRIDE_CONFIG_APEDMAR 0x14f8 122 #define MC_TXN_OVERRIDE_CONFIG_NVENCSRD 0x10e0 123 #define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB 0x1318 124 #define MC_TXN_OVERRIDE_CONFIG_VICSRD1 0x1510 125 #define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR 0x14a8 126 #define MC_TXN_OVERRIDE_CONFIG_VIW 0x1390 127 #define MC_TXN_OVERRIDE_CONFIG_SDMMCRAA 0x1308 128 #define MC_TXN_OVERRIDE_CONFIG_AXISW 0x1468 129 #define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR 0x1260 130 #define MC_TXN_OVERRIDE_CONFIG_UFSHCR 0x1480 131 #define MC_TXN_OVERRIDE_CONFIG_TSECSWR 0x12a8 132 #define MC_TXN_OVERRIDE_CONFIG_GPUSWR 0x12c8 133 #define MC_TXN_OVERRIDE_CONFIG_SATAR 0x10f8 134 #define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW 0x1258 135 #define MC_TXN_OVERRIDE_CONFIG_TSECSWRB 0x1438 136 #define MC_TXN_OVERRIDE_CONFIG_GPUSRD2 0x1440 137 #define MC_TXN_OVERRIDE_CONFIG_SCEDMAR 0x14e8 138 #define MC_TXN_OVERRIDE_CONFIG_GPUSWR2 0x1448 139 #define MC_TXN_OVERRIDE_CONFIG_AONDMAW 0x14d0 140 #define MC_TXN_OVERRIDE_CONFIG_APEDMAW 0x1500 141 #define MC_TXN_OVERRIDE_CONFIG_AONW 0x14c0 142 #define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR 0x10b0 143 #define MC_TXN_OVERRIDE_CONFIG_ETRR 0x1420 144 #define MC_TXN_OVERRIDE_CONFIG_SESWR 0x1408 145 #define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD 0x13f0 146 #define MC_TXN_OVERRIDE_CONFIG_NVDECSRD 0x13c0 147 #define MC_TXN_OVERRIDE_CONFIG_TSECSRDB 0x1430 148 #define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW 0x14b0 149 #define MC_TXN_OVERRIDE_CONFIG_APER 0x13d0 150 #define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1 0x1518 151 #define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR 0x1250 152 #define MC_TXN_OVERRIDE_CONFIG_ISPWA 0x1230 153 #define MC_TXN_OVERRIDE_CONFIG_SESRD 0x1400 154 #define MC_TXN_OVERRIDE_CONFIG_SCER 0x14d8 155 #define MC_TXN_OVERRIDE_CONFIG_AONR 0x14b8 156 #define MC_TXN_OVERRIDE_CONFIG_MPCORER 0x1138 157 #define MC_TXN_OVERRIDE_CONFIG_SDMMCWA 0x1320 158 #define MC_TXN_OVERRIDE_CONFIG_HDAW 0x11a8 159 #define MC_TXN_OVERRIDE_CONFIG_NVDECSWR 0x13c8 160 #define MC_TXN_OVERRIDE_CONFIG_UFSHCW 0x1488 161 #define MC_TXN_OVERRIDE_CONFIG_AONDMAR 0x14c8 162 #define MC_TXN_OVERRIDE_CONFIG_SATAW 0x11e8 163 #define MC_TXN_OVERRIDE_CONFIG_ETRW 0x1428 164 #define MC_TXN_OVERRIDE_CONFIG_VICSWR 0x1368 165 #define MC_TXN_OVERRIDE_CONFIG_NVENCSWR 0x1158 166 #define MC_TXN_OVERRIDE_CONFIG_AFIR 0x1070 167 #define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB 0x1338 168 #define MC_TXN_OVERRIDE_CONFIG_SDMMCRA 0x1300 169 #define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1 0x1508 170 #define MC_TXN_OVERRIDE_CONFIG_ISPWB 0x1238 171 #define MC_TXN_OVERRIDE_CONFIG_BPMPR 0x1498 172 #define MC_TXN_OVERRIDE_CONFIG_APEW 0x13d8 173 #define MC_TXN_OVERRIDE_CONFIG_SDMMCR 0x1310 174 #define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW 0x1268 175 #define MC_TXN_OVERRIDE_CONFIG_TSECSRD 0x12a0 176 #define MC_TXN_OVERRIDE_CONFIG_AFIW 0x1188 177 #define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0 178 179 /******************************************************************************* 180 * Structure to hold the transaction override settings to use to override 181 * client inputs 182 ******************************************************************************/ 183 typedef struct mc_txn_override_cfg { 184 uint32_t offset; 185 uint8_t cgid_tag; 186 } mc_txn_override_cfg_t; 187 188 #define mc_make_txn_override_cfg(off, val) \ 189 { \ 190 .offset = MC_TXN_OVERRIDE_CONFIG_ ## off, \ 191 .cgid_tag = MC_TXN_OVERRIDE_ ## val \ 192 } 193 194 /******************************************************************************* 195 * Structure to hold the Stream ID to use to override client inputs 196 ******************************************************************************/ 197 typedef struct mc_streamid_override_cfg { 198 uint32_t offset; 199 uint8_t stream_id; 200 } mc_streamid_override_cfg_t; 201 202 /******************************************************************************* 203 * Structure to hold the Stream ID Security Configuration settings 204 ******************************************************************************/ 205 typedef struct mc_streamid_security_cfg { 206 char *name; 207 uint32_t offset; 208 int override_enable; 209 int override_client_inputs; 210 int override_client_ns_flag; 211 } mc_streamid_security_cfg_t; 212 213 #define OVERRIDE_DISABLE 1 214 #define OVERRIDE_ENABLE 0 215 #define CLIENT_FLAG_SECURE 0 216 #define CLIENT_FLAG_NON_SECURE 1 217 #define CLIENT_INPUTS_OVERRIDE 1 218 #define CLIENT_INPUTS_NO_OVERRIDE 0 219 220 #define mc_make_sec_cfg(off, ns, ovrrd, access) \ 221 { \ 222 .name = # off, \ 223 .offset = MC_STREAMID_OVERRIDE_TO_SECURITY_CFG( \ 224 MC_STREAMID_OVERRIDE_CFG_ ## off), \ 225 .override_client_ns_flag = CLIENT_FLAG_ ## ns, \ 226 .override_client_inputs = CLIENT_INPUTS_ ## ovrrd, \ 227 .override_enable = OVERRIDE_ ## access \ 228 } 229 230 /******************************************************************************* 231 * Structure to hold Memory Controller's Configuration settings 232 ******************************************************************************/ 233 typedef struct tegra_mc_settings { 234 const uint32_t *streamid_override_cfg; 235 uint32_t num_streamid_override_cfgs; 236 const mc_streamid_security_cfg_t *streamid_security_cfg; 237 uint32_t num_streamid_security_cfgs; 238 const mc_txn_override_cfg_t *txn_override_cfg; 239 uint32_t num_txn_override_cfgs; 240 } tegra_mc_settings_t; 241 242 #endif /* __ASSEMBLY__ */ 243 244 /******************************************************************************* 245 * Memory Controller SMMU Bypass config register 246 ******************************************************************************/ 247 #define MC_SMMU_BYPASS_CONFIG 0x1820 248 #define MC_SMMU_BYPASS_CTRL_MASK 0x3 249 #define MC_SMMU_BYPASS_CTRL_SHIFT 0 250 #define MC_SMMU_CTRL_TBU_BYPASS_ALL (0 << MC_SMMU_BYPASS_CTRL_SHIFT) 251 #define MC_SMMU_CTRL_TBU_RSVD (1 << MC_SMMU_BYPASS_CTRL_SHIFT) 252 #define MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID (2 << MC_SMMU_BYPASS_CTRL_SHIFT) 253 #define MC_SMMU_CTRL_TBU_BYPASS_NONE (3 << MC_SMMU_BYPASS_CTRL_SHIFT) 254 #define MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT (1 << 31) 255 #define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \ 256 MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID) 257 258 #define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID (1 << 0) 259 #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV (2 << 4) 260 #define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT (1 << 12) 261 262 /******************************************************************************* 263 * Non-SO_DEV transactions override values for CGID_TAG bitfield for the 264 * MC_TXN_OVERRIDE_CONFIG_{module} registers 265 ******************************************************************************/ 266 #define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT 0 267 #define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID 1 268 #define MC_TXN_OVERRIDE_CGID_TAG_ZERO 2 269 #define MC_TXN_OVERRIDE_CGID_TAG_ADR 3 270 #define MC_TXN_OVERRIDE_CGID_TAG_MASK 3 271 272 /******************************************************************************* 273 * Memory Controller Reset Control registers 274 ******************************************************************************/ 275 #define MC_CLIENT_HOTRESET_CTRL0 0x200 276 #define MC_CLIENT_HOTRESET_CTRL0_RESET_VAL 0 277 #define MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB (1 << 0) 278 #define MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB (1 << 6) 279 #define MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB (1 << 7) 280 #define MC_CLIENT_HOTRESET_CTRL0_ISP2_FLUSH_ENB (1 << 8) 281 #define MC_CLIENT_HOTRESET_CTRL0_MPCORE_FLUSH_ENB (1 << 9) 282 #define MC_CLIENT_HOTRESET_CTRL0_NVENC_FLUSH_ENB (1 << 11) 283 #define MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB (1 << 15) 284 #define MC_CLIENT_HOTRESET_CTRL0_VI_FLUSH_ENB (1 << 17) 285 #define MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB (1 << 18) 286 #define MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB (1 << 19) 287 #define MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB (1 << 20) 288 #define MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB (1 << 22) 289 #define MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB (1 << 29) 290 #define MC_CLIENT_HOTRESET_CTRL0_SDMMC2A_FLUSH_ENB (1 << 30) 291 #define MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB (1 << 31) 292 #define MC_CLIENT_HOTRESET_STATUS0 0x204 293 #define MC_CLIENT_HOTRESET_CTRL1 0x970 294 #define MC_CLIENT_HOTRESET_CTRL1_RESET_VAL 0 295 #define MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB (1 << 0) 296 #define MC_CLIENT_HOTRESET_CTRL1_GPU_FLUSH_ENB (1 << 2) 297 #define MC_CLIENT_HOTRESET_CTRL1_NVDEC_FLUSH_ENB (1 << 5) 298 #define MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB (1 << 6) 299 #define MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB (1 << 7) 300 #define MC_CLIENT_HOTRESET_CTRL1_NVJPG_FLUSH_ENB (1 << 8) 301 #define MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB (1 << 12) 302 #define MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB (1 << 13) 303 #define MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB (1 << 18) 304 #define MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB (1 << 19) 305 #define MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB (1 << 20) 306 #define MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB (1 << 21) 307 #define MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB (1 << 22) 308 #define MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB (1 << 23) 309 #define MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB (1 << 24) 310 #define MC_CLIENT_HOTRESET_STATUS1 0x974 311 312 /******************************************************************************* 313 * Memory Controller's PCFIFO client configuration registers 314 ******************************************************************************/ 315 #define MC_PCFIFO_CLIENT_CONFIG1 0xdd4 316 #define MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL 0x20000 317 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_UNORDERED (0 << 17) 318 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_MASK (1 << 17) 319 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_UNORDERED (0 << 21) 320 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_MASK (1 << 21) 321 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_UNORDERED (0 << 29) 322 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_MASK (1 << 29) 323 324 #define MC_PCFIFO_CLIENT_CONFIG2 0xdd8 325 #define MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL 0x20000 326 #define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_UNORDERED (0 << 11) 327 #define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_MASK (1 << 11) 328 #define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_UNORDERED (0 << 13) 329 #define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_MASK (1 << 13) 330 331 #define MC_PCFIFO_CLIENT_CONFIG3 0xddc 332 #define MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL 0 333 #define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_UNORDERED (0 << 7) 334 #define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_MASK (1 << 7) 335 336 #define MC_PCFIFO_CLIENT_CONFIG4 0xde0 337 #define MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL 0 338 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_UNORDERED (0 << 1) 339 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_MASK (1 << 1) 340 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_UNORDERED (0 << 5) 341 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_MASK (1 << 5) 342 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_UNORDERED (0 << 13) 343 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_MASK (1 << 13) 344 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_UNORDERED (0 << 15) 345 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_MASK (1 << 15) 346 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_UNORDERED (0 << 17) 347 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_MASK (1 << 17) 348 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_UNORDERED (0 << 22) 349 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_MASK (1 << 22) 350 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_UNORDERED (0 << 26) 351 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_MASK (1 << 26) 352 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_UNORDERED (0 << 30) 353 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_MASK (1 << 30) 354 355 #define MC_PCFIFO_CLIENT_CONFIG5 0xbf4 356 #define MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL 0 357 #define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_UNORDERED (0 << 0) 358 #define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_MASK (1 << 0) 359 360 /******************************************************************************* 361 * Memory Controller's SMMU client configuration registers 362 ******************************************************************************/ 363 #define MC_SMMU_CLIENT_CONFIG1 0x44 364 #define MC_SMMU_CLIENT_CONFIG1_RESET_VAL 0x20000 365 #define MC_SMMU_CLIENT_CONFIG1_AFIW_UNORDERED (0 << 17) 366 #define MC_SMMU_CLIENT_CONFIG1_AFIW_MASK (1 << 17) 367 #define MC_SMMU_CLIENT_CONFIG1_HDAW_UNORDERED (0 << 21) 368 #define MC_SMMU_CLIENT_CONFIG1_HDAW_MASK (1 << 21) 369 #define MC_SMMU_CLIENT_CONFIG1_SATAW_UNORDERED (0 << 29) 370 #define MC_SMMU_CLIENT_CONFIG1_SATAW_MASK (1 << 29) 371 372 #define MC_SMMU_CLIENT_CONFIG2 0x48 373 #define MC_SMMU_CLIENT_CONFIG2_RESET_VAL 0x20000 374 #define MC_SMMU_CLIENT_CONFIG2_XUSB_HOSTW_UNORDERED (0 << 11) 375 #define MC_SMMU_CLIENT_CONFIG2_XUSB_HOSTW_MASK (1 << 11) 376 #define MC_SMMU_CLIENT_CONFIG2_XUSB_DEVW_UNORDERED (0 << 13) 377 #define MC_SMMU_CLIENT_CONFIG2_XUSB_DEVW_MASK (1 << 13) 378 379 #define MC_SMMU_CLIENT_CONFIG3 0x4c 380 #define MC_SMMU_CLIENT_CONFIG3_RESET_VAL 0 381 #define MC_SMMU_CLIENT_CONFIG3_SDMMCWAB_UNORDERED (0 << 7) 382 #define MC_SMMU_CLIENT_CONFIG3_SDMMCWAB_MASK (1 << 7) 383 384 #define MC_SMMU_CLIENT_CONFIG4 0xb9c 385 #define MC_SMMU_CLIENT_CONFIG4_RESET_VAL 0 386 #define MC_SMMU_CLIENT_CONFIG4_SESWR_UNORDERED (0 << 1) 387 #define MC_SMMU_CLIENT_CONFIG4_SESWR_MASK (1 << 1) 388 #define MC_SMMU_CLIENT_CONFIG4_ETRW_UNORDERED (0 << 5) 389 #define MC_SMMU_CLIENT_CONFIG4_ETRW_MASK (1 << 5) 390 #define MC_SMMU_CLIENT_CONFIG4_AXISW_UNORDERED (0 << 13) 391 #define MC_SMMU_CLIENT_CONFIG4_AXISW_MASK (1 << 13) 392 #define MC_SMMU_CLIENT_CONFIG4_EQOSW_UNORDERED (0 << 15) 393 #define MC_SMMU_CLIENT_CONFIG4_EQOSW_MASK (1 << 15) 394 #define MC_SMMU_CLIENT_CONFIG4_UFSHCW_UNORDERED (0 << 17) 395 #define MC_SMMU_CLIENT_CONFIG4_UFSHCW_MASK (1 << 17) 396 #define MC_SMMU_CLIENT_CONFIG4_BPMPDMAW_UNORDERED (0 << 22) 397 #define MC_SMMU_CLIENT_CONFIG4_BPMPDMAW_MASK (1 << 22) 398 #define MC_SMMU_CLIENT_CONFIG4_AONDMAW_UNORDERED (0 << 26) 399 #define MC_SMMU_CLIENT_CONFIG4_AONDMAW_MASK (1 << 26) 400 #define MC_SMMU_CLIENT_CONFIG4_SCEDMAW_UNORDERED (0 << 30) 401 #define MC_SMMU_CLIENT_CONFIG4_SCEDMAW_MASK (1 << 30) 402 403 #define MC_SMMU_CLIENT_CONFIG5 0xbac 404 #define MC_SMMU_CLIENT_CONFIG5_RESET_VAL 0 405 #define MC_SMMU_CLIENT_CONFIG5_APEDMAW_UNORDERED (0 << 0) 406 #define MC_SMMU_CLIENT_CONFIG5_APEDMAW_MASK (1 << 0) 407 408 #ifndef __ASSEMBLY__ 409 410 #include <mmio.h> 411 412 static inline uint32_t tegra_mc_read_32(uint32_t off) 413 { 414 return mmio_read_32(TEGRA_MC_BASE + off); 415 } 416 417 static inline void tegra_mc_write_32(uint32_t off, uint32_t val) 418 { 419 mmio_write_32(TEGRA_MC_BASE + off, val); 420 } 421 422 static inline uint32_t tegra_mc_streamid_read_32(uint32_t off) 423 { 424 return mmio_read_32(TEGRA_MC_STREAMID_BASE + off); 425 } 426 427 static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val) 428 { 429 mmio_write_32(TEGRA_MC_STREAMID_BASE + off, val); 430 } 431 432 #define mc_set_pcfifo_unordered_boot_so_mss(id, client) \ 433 (~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \ 434 MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED) 435 436 #define mc_set_smmu_unordered_boot_so_mss(id, client) \ 437 (~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \ 438 MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED) 439 440 #define mc_set_tsa_passthrough(client) \ 441 { \ 442 mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \ 443 (TSA_CONFIG_STATIC0_CSW_##client##_RESET & \ 444 ~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \ 445 TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \ 446 } 447 448 #define mc_set_forced_coherent_cfg(client) \ 449 { \ 450 tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \ 451 MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV); \ 452 } 453 454 #define mc_set_forced_coherent_so_dev_cfg(client) \ 455 { \ 456 tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \ 457 MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV | \ 458 MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT); \ 459 } 460 461 #define mc_set_forced_coherent_axid_so_dev_cfg(client) \ 462 { \ 463 tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \ 464 MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV | \ 465 MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID | \ 466 MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT); \ 467 } 468 469 /******************************************************************************* 470 * Handler to read memory configuration settings 471 * 472 * Implemented by SoCs under tegra/soc/txxx 473 ******************************************************************************/ 474 tegra_mc_settings_t *tegra_get_mc_settings(void); 475 476 #endif /* __ASSMEBLY__ */ 477 478 #endif /* __MEMCTRLV2_H__ */ 479
