1 /** @file 2 3 Differentiated System Description Table Fields (DSDT) 4 5 Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> 6 Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR> 7 8 This program and the accompanying materials 9 are licensed and made available under the terms and conditions of the BSD License 10 which accompanies this distribution. The full text of the license may be found at 11 http://opensource.org/licenses/bsd-license.php 12 13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 15 16 **/ 17 /** 18 19 Derived from: 20 ArmPlatformPkg/ArmJunoPkg/AcpiTables/Dsdt.asl 21 22 **/ 23 24 DefinitionBlock ("DSDT.aml", "DSDT", 2, "AMDINC", "SEATTLE ", 3) 25 { 26 Scope (_SB) 27 { 28 Device (CPU0) 29 { 30 Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID 31 Name (_UID, 0x000) // _UID: Unique ID 32 } 33 #if (NUM_CORES > 1) 34 Device (CPU1) 35 { 36 Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID 37 Name (_UID, 0x001) // _UID: Unique ID 38 } 39 #endif 40 #if (NUM_CORES > 2) 41 Device (CPU2) 42 { 43 Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID 44 Name (_UID, 0x100) // _UID: Unique ID 45 } 46 #endif 47 #if (NUM_CORES > 3) 48 Device (CPU3) 49 { 50 Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID 51 Name (_UID, 0x101) // _UID: Unique ID 52 } 53 #endif 54 #if (NUM_CORES > 4) 55 Device (CPU4) 56 { 57 Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID 58 Name (_UID, 0x200) // _UID: Unique ID 59 } 60 #endif 61 #if (NUM_CORES > 5) 62 Device (CPU5) 63 { 64 Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID 65 Name (_UID, 0x201) // _UID: Unique ID 66 } 67 #endif 68 #if (NUM_CORES > 6) 69 Device (CPU6) 70 { 71 Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID 72 Name (_UID, 0x300) // _UID: Unique ID 73 } 74 #endif 75 #if (NUM_CORES > 7) 76 Device (CPU7) 77 { 78 Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID 79 Name (_UID, 0x301) // _UID: Unique ID 80 } 81 #endif 82 83 Device (AHC0) 84 { 85 Name (_HID, "AMDI0600") // _HID: Hardware ID 86 Name (_UID, 0x00) // _UID: Unique ID 87 Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute 88 Name (_CLS, Package (0x03) // _CLS: Class Code 89 { 90 0x01, 91 0x06, 92 0x01 93 }) 94 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings 95 { 96 Memory32Fixed (ReadWrite, 97 0xE0300000, // Address Base (MMIO) 98 0x00010000, // Address Length 99 ) 100 Memory32Fixed (ReadWrite, 101 0xE0000078, // Address Base (SGPIO) 102 0x00000001, // Address Length 103 ) 104 Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000183, } 105 }) 106 } 107 108 Device (AHC1) 109 { 110 Name (_HID, "AMDI0600") // _HID: Hardware ID 111 Name (_UID, 0x01) // _UID: Unique ID 112 Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute 113 Name (_CLS, Package (0x03) // _CLS: Class Code 114 { 115 0x01, 116 0x06, 117 0x01 118 }) 119 Method (_STA) 120 { 121 Return (0x0F) 122 } 123 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings 124 { 125 Memory32Fixed (ReadWrite, 126 0xE0D00000, // Address Base (MMIO) 127 0x00010000, // Address Length 128 ) 129 Memory32Fixed (ReadWrite, 130 0xE000007C, // Address Base (SGPIO) 131 0x00000001, // Address Length 132 ) 133 Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000182, } 134 }) 135 } 136 137 #if DO_XGBE 138 Device (ETH0) 139 { 140 Name (_HID, "AMDI8001") // _HID: Hardware ID 141 Name (_UID, 0x00) // _UID: Unique ID 142 Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute 143 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings 144 145 { 146 Memory32Fixed (ReadWrite, 147 0xE0700000, // Address Base (XGMAC) 148 0x00010000, // Address Length 149 ) 150 Memory32Fixed (ReadWrite, 151 0xE0780000, // Address Base (XPCS) 152 0x00080000, // Address Length 153 ) 154 Memory32Fixed (ReadWrite, 155 0xE1240800, // Address Base (SERDES_RxTx) 156 0x00000400, // Address Length 157 ) 158 Memory32Fixed (ReadWrite, 159 0xE1250000, // Address Base (SERDES_IR_1) 160 0x00000060, // Address Length 161 ) 162 Memory32Fixed (ReadWrite, 163 0xE12500F8, // Address Base (SERDES_IR_2) 164 0x00000004, // Address Length 165 ) 166 Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000165, } // XGMAC 167 Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x0000017A, } // DMA0 168 Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x0000017B, } // DMA1 169 Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x0000017C, } // DMA2 170 Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x0000017D, } // DMA3 171 Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000163, } // XPCS 172 }) 173 Name (_DSD, Package (0x02) // _DSD: Device-Specific Data 174 { 175 ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), 176 Package () 177 { 178 Package (0x02) {"mac-address", Package (0x06) {0x02, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5}}, 179 Package (0x02) {"phy-mode", "xgmii"}, 180 Package (0x02) {"amd,speed-set", 0x00}, 181 Package (0x02) {"amd,dma-freq", 0x0EE6B280}, 182 Package (0x02) {"amd,ptp-freq", 0x0EE6B280}, 183 Package (0x02) {"amd,serdes-blwc", Package (0x03) {1, 1, 0}}, 184 Package (0x02) {"amd,serdes-cdr-rate", Package (0x03) {2, 2, 7}}, 185 Package (0x02) {"amd,serdes-pq-skew", Package (0x03) {10, 10, 18}}, 186 Package (0x02) {"amd,serdes-tx-amp", Package (0x03) {15, 15, 10}}, 187 Package (0x02) {"amd,serdes-dfe-tap-config", Package (0x03) {3, 3, 1}}, 188 Package (0x02) {"amd,serdes-dfe-tap-enable", Package (0x03) {0, 0, 127}}, 189 Package (0x02) {"amd,per-channel-interrupt", 0x01} 190 } 191 }) 192 } 193 194 Device (ETH1) 195 { 196 Name (_HID, "AMDI8001") // _HID: Hardware ID 197 Name (_UID, 0x01) // _UID: Unique ID 198 Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute 199 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings 200 { 201 Memory32Fixed (ReadWrite, 202 0xE0900000, // Address Base (XGMAC) 203 0x00010000, // Address Length 204 ) 205 Memory32Fixed (ReadWrite, 206 0xE0980000, // Address Base (XPCS) 207 0x00080000, // Address Length 208 ) 209 Memory32Fixed (ReadWrite, 210 0xE1240C00, // Address Base (SERDES_RxTx) 211 0x00000400, // Address Length 212 ) 213 Memory32Fixed (ReadWrite, 214 0xE1250080, // Address Base (SERDES_IR_1) 215 0x00000060, // Address Length 216 ) 217 Memory32Fixed (ReadWrite, 218 0xE12500FC, // Address Base (SERDES_IR_2) 219 0x00000004, // Address Length 220 ) 221 Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000164, } // XGMAC 222 Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x00000175, } // DMA0 223 Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x00000176, } // DMA1 224 Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x00000177, } // DMA2 225 Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x00000178, } // DMA3 226 Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000162, } // XPCS 227 }) 228 Name (_DSD, Package (0x02) // _DSD: Device-Specific Data 229 { 230 ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), 231 Package () 232 { 233 Package (0x02) {"mac-address", Package (0x06) {0x02, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5}}, 234 Package (0x02) {"phy-mode", "xgmii"}, 235 Package (0x02) {"amd,speed-set", 0x00}, 236 Package (0x02) {"amd,dma-freq", 0x0EE6B280}, 237 Package (0x02) {"amd,ptp-freq", 0x0EE6B280}, 238 Package (0x02) {"amd,serdes-blwc", Package (0x03) {1, 1, 0}}, 239 Package (0x02) {"amd,serdes-cdr-rate", Package (0x03) {2, 2, 7}}, 240 Package (0x02) {"amd,serdes-pq-skew", Package (0x03) {10, 10, 18}}, 241 Package (0x02) {"amd,serdes-tx-amp", Package (0x03) {15, 15, 10}}, 242 Package (0x02) {"amd,serdes-dfe-tap-config", Package (0x03) {3, 3, 1}}, 243 Package (0x02) {"amd,serdes-dfe-tap-enable", Package (0x03) {0, 0, 127}}, 244 Package (0x02) {"amd,per-channel-interrupt", 0x01} 245 } 246 }) 247 } 248 #endif // DO_XGBE 249 250 Device (SPI0) 251 { 252 Name (_HID, "AMDI0500") // _HID: Hardware ID 253 Name (_UID, 0x00) // _UID: Unique ID 254 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings 255 { 256 Memory32Fixed (ReadWrite, 257 0xE1020000, // Address Base 258 0x00001000, // Address Length 259 ) 260 Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000016A, } 261 }) 262 } 263 264 Device (SPI1) 265 { 266 Name (_HID, "AMDI0500") // _HID: Hardware ID 267 Name (_UID, 0x01) // _UID: Unique ID 268 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings 269 { 270 Memory32Fixed (ReadWrite, 271 0xE1030000, // Address Base 272 0x00001000, // Address Length 273 ) 274 Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000169, } 275 }) 276 277 Device(SDC0) 278 { 279 Name(_HID, "AMDI0501") // SD Card/MMC slot 280 Name(_CRS, ResourceTemplate() 281 { 282 SPISerialBus(1, // DeviceSelection 283 PolarityLow, // DeviceSelectionPolarity 284 FourWireMode, // WireMode 285 8, // DataBitLength 286 ControllerInitiated, // SlaveMode 287 20000000, // ConnectionSpeed 288 ClockPolarityLow, // ClockPolarity 289 ClockPhaseFirst, // ClockPhase 290 "\\SB.SPI1", // ResourceSource 291 0, // ResourceSourceIndex 292 ResourceConsumer, // ResourceUsage 293 ) // SPISerialBus() 294 295 // SD Card Detect signal 296 GpioInt(Edge, ActiveBoth, ExclusiveAndWake, PullDown, , "\\_SB.GIO1") {6} 297 }) // ResourceTemplate() 298 299 } // Device() 300 } 301 302 Device (COM1) 303 { 304 Name (_HID, "AMDI0511") // _HID: Hardware ID 305 Name (_CID, "ARMH0011") // _CID: Compatible ID 306 Name (_ADR, 0xE1010000) // _ADR: Address 307 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings 308 { 309 Memory32Fixed (ReadWrite, 310 0xE1010000, // Address Base 311 0x00001000, // Address Length 312 ) 313 Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000168, } 314 }) 315 } 316 317 Device (GIO0) 318 { 319 Name (_HID, "AMDI0400") // _HID: Hardware ID 320 Name (_CID, "ARMH0061") // _CID: Compatible ID 321 Name (_UID, 0x00) // _UID: Unique ID 322 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings 323 { 324 Memory32Fixed (ReadWrite, 325 0xE0080000, // Address Base 326 0x00001000, // Address Length 327 ) 328 Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000189, } 329 }) 330 } 331 332 Device (GIO1) 333 { 334 Name (_HID, "AMDI0400") // _HID: Hardware ID 335 Name (_CID, "ARMH0061") // _CID: Compatible ID 336 Name (_UID, 0x01) // _UID: Unique ID 337 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings 338 { 339 Memory32Fixed (ReadWrite, 340 0xE1050000, // Address Base 341 0x00001000, // Address Length 342 ) 343 Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000186, } 344 }) 345 } 346 347 Device (GIO2) 348 { 349 Name (_HID, "AMDI0400") // _HID: Hardware ID 350 Name (_CID, "ARMH0061") // _CID: Compatible ID 351 Name (_UID, 0x02) // _UID: Unique ID 352 Method (_STA) 353 { 354 Return (0x0F) 355 } 356 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings 357 { 358 Memory32Fixed (ReadWrite, 359 0xE0020000, // Address Base 360 0x00001000, // Address Length 361 ) 362 Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000018E, } 363 }) 364 } 365 366 Device (GIO3) 367 { 368 Name (_HID, "AMDI0400") // _HID: Hardware ID 369 Name (_CID, "ARMH0061") // _CID: Compatible ID 370 Name (_UID, 0x03) // _UID: Unique ID 371 Method (_STA) 372 { 373 Return (0x0F) 374 } 375 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings 376 { 377 Memory32Fixed (ReadWrite, 378 0xE0030000, // Address Base 379 0x00001000, // Address Length 380 ) 381 Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000018D, } 382 }) 383 } 384 385 Device (I2C0) 386 { 387 Name (_HID, "AMDI0510") // _HID: Hardware ID 388 Name (_UID, 0x00) // _UID: Unique ID 389 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings 390 { 391 Memory32Fixed (ReadWrite, 392 0xE1000000, // Address Base 393 0x00001000, // Address Length 394 ) 395 Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000185, } 396 }) 397 398 Method (SSCN, 0, NotSerialized) 399 { 400 Return (Package (0x03) 401 { 402 0x0430, 403 0x04E1, 404 0x00 405 }) 406 } 407 408 Method (FMCN, 0, NotSerialized) 409 { 410 Return (Package (0x03) 411 { 412 0x00DE, 413 0x018F, 414 0x00 415 }) 416 } 417 } 418 419 Device (I2C1) 420 { 421 Name (_HID, "AMDI0510") // _HID: Hardware ID 422 Name (_UID, 0x01) // _UID: Unique ID 423 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings 424 { 425 Memory32Fixed (ReadWrite, 426 0xE0050000, // Address Base 427 0x00001000, // Address Length 428 ) 429 Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000174, } 430 }) 431 432 Method (SSCN, 0, NotSerialized) 433 { 434 Return (Package (0x03) 435 { 436 0x0430, 437 0x04E1, 438 0x00 439 }) 440 } 441 442 Method (FMCN, 0, NotSerialized) 443 { 444 Return (Package (0x03) 445 { 446 0x00DE, 447 0x018F, 448 0x00 449 }) 450 } 451 } 452 453 Device (CCP0) 454 { 455 Name (_HID, "AMDI0C00") // _HID: Hardware ID 456 Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute 457 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings 458 { 459 Memory32Fixed (ReadWrite, 460 0xE0100000, // Address Base 461 0x00010000, // Address Length 462 ) 463 Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000023, } 464 }) 465 466 Name (_DSD, Package (0x02) // _DSD: Device-Specific Data 467 { 468 ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), 469 Package () 470 { 471 Package (0x02) {"amd,zlib-support", 1} 472 } 473 }) 474 } 475 476 #if DO_KCS 477 // 478 // IPMI/KCS 479 // 480 Device (KCS0) 481 { 482 Name (_HID, "AMDI0300") 483 Name (_CID, "IPI0001") 484 Name (_STR, Unicode("IPMI_KCS")) 485 Name (_UID, 0) 486 Name (_CRS, ResourceTemplate() { 487 Memory32Fixed(ReadWrite, 0xE0010000, 0x1) // KCS Data In/Out 488 Memory32Fixed(ReadWrite, 0xE0010004, 0x1) // KCS Control/Status 489 Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,,,) { 421 } // GSIV 490 }) 491 Method (_IFT) { // Interface Type 492 Return ( 0x01) // IPMI KCS 493 } 494 495 Method (_SRV) { // Spec Revision 496 Return (0x200) // IPMI Spec v2.0 497 } 498 } 499 #endif // DO_KCS 500 501 // 502 // PCIe Root Bus 503 // 504 Device (PCI0) 505 { 506 Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID 507 Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID 508 Name (_SEG, 0x00) // _SEG: PCI Segment 509 Name (_BBN, 0x00) // _BBN: BIOS Bus Number 510 Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute 511 Name (_PRT, Package (0x04) // _PRT: PCI Routing Table 512 { 513 Package (0x04) 514 { 515 0xFFFF, 516 0x00, 517 0x00, 518 0x0140 519 }, 520 521 Package (0x04) 522 { 523 0xFFFF, 524 0x01, 525 0x00, 526 0x0141 527 }, 528 529 Package (0x04) 530 { 531 0xFFFF, 532 0x02, 533 0x00, 534 0x0142 535 }, 536 537 Package (0x04) 538 { 539 0xFFFF, 540 0x03, 541 0x00, 542 0x0143 543 } 544 }) // _PRT 545 546 Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings 547 { 548 Name (RBUF, ResourceTemplate () 549 { 550 WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, 551 0x0000, // Granularity 552 0x0000, // Range Minimum 553 0x007F, // Range Maximum 554 0x0000, // Translation Offset 555 0x0080, // Length 556 ) 557 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, 558 0x00000000, // Granularity 559 0x40000000, // Range Minimum 560 0x5FFFFFFF, // Range Maximum 561 0x00000000, // Translation Offset 562 0x20000000 // Length 563 ) 564 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, 565 0x00000000, // Granularity 566 0x60000000, // Range Minimum 567 0x7FFFFFFF, // Range Maximum 568 0x00000000, // Translation Offset 569 0x20000000 // Length 570 ) 571 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, 572 0x00000000, // Granularity 573 0x80000000, // Range Minimum 574 0x9FFFFFFF, // Range Maximum 575 0x00000000, // Translation Offset 576 0x20000000 // Length 577 ) 578 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, 579 0x00000000, // Granularity 580 0xA0000000, // Range Minimum 581 0xBFFFFFFF, // Range Maximum 582 0x00000000, // Translation Offset 583 0x20000000 // Length 584 ) 585 QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, 586 0x0000000000000000, // Granularity 587 0x0000000100000000, // Range Minimum 588 0x00000001FFFFFFFF, // Range Maximum 589 0x0000000000000000, // Translation Offset 590 0x0000000100000000 // Length 591 ) 592 QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, 593 0x0000000000000000, // Granularity 594 0x0000000200000000, // Range Minimum 595 0x00000003FFFFFFFF, // Range Maximum 596 0x0000000000000000, // Translation Offset 597 0x0000000200000000 // Length 598 ) 599 QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, 600 0x0000000000000000, // Granularity 601 0x0000000400000000, // Range Minimum 602 0x00000007FFFFFFFF, // Range Maximum 603 0x0000000000000000, // Translation Offset 604 0x0000000400000000 // Length 605 ) 606 QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, 607 0x0000000000000000, // Granularity 608 0x0000000800000000, // Range Minimum 609 0x0000000FFFFFFFFF, // Range Maximum 610 0x0000000000000000, // Translation Offset 611 0x0000000800000000 // Length 612 ) 613 QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, 614 0x0000000000000000, // Granularity 615 0x0000001000000000, // Range Minimum 616 0x0000001FFFFFFFFF, // Range Maximum 617 0x0000000000000000, // Translation Offset 618 0x0000001000000000 // Length 619 ) 620 QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, 621 0x0000000000000000, // Granularity 622 0x0000002000000000, // Range Minimum 623 0x0000003FFFFFFFFF, // Range Maximum 624 0x0000000000000000, // Translation Offset 625 0x0000002000000000 // Length 626 ) 627 QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, 628 0x0000000000000000, // Granularity 629 0x0000004000000000, // Range Minimum 630 0x0000007FFFFFFFFF, // Range Maximum 631 0x0000000000000000, // Translation Offset 632 0x0000004000000000 // Length 633 ) 634 DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 635 0x00000000, // Granularity 636 0x00000000, // Range Minimum 637 0x0000FFFF, // Range Maximum 638 0xEFFF0000, // Translation Address 639 0x00010000, // Length 640 , 641 , 642 , 643 TypeTranslation 644 ) 645 }) 646 Return (RBUF) /* \_SB_.PCI0._CRS.RBUF */ 647 } // Method(_CRS) 648 649 Device (RES0) 650 { 651 Name (_HID, "PNP0C02") 652 Name (_CRS, ResourceTemplate () 653 { 654 Memory32Fixed (ReadWrite, 0xF0000000, 0x8000000) 655 }) 656 } 657 Name (SUPP, 0x00) 658 Name (CTRL, 0x00) 659 Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities 660 { 661 CreateDWordField (Arg3, 0x00, CDW1) 662 If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) 663 { 664 CreateDWordField (Arg3, 0x04, CDW2) 665 CreateDWordField (Arg3, 0x08, CDW3) 666 Store (CDW2, SUPP) /* \_SB_.PCI0.SUPP */ 667 Store (CDW3, CTRL) /* \_SB_.PCI0.CTRL */ 668 If (LNotEqual (And (SUPP, 0x16), 0x16)) 669 { 670 And (CTRL, 0x1E, CTRL) /* \_SB_.PCI0.CTRL */ 671 } 672 673 And (CTRL, 0x1D, CTRL) /* \_SB_.PCI0.CTRL */ 674 If (LNotEqual (Arg1, One)) 675 { 676 Or (CDW1, 0x08, CDW1) /* \_SB_.PCI0._OSC.CDW1 */ 677 } 678 679 If (LNotEqual (CDW3, CTRL)) 680 { 681 Or (CDW1, 0x10, CDW1) /* \_SB_.PCI0._OSC.CDW1 */ 682 } 683 684 Store (CTRL, CDW3) /* \_SB_.PCI0._OSC.CDW3 */ 685 Return (Arg3) 686 } 687 Else 688 { 689 Or (CDW1, 0x04, CDW1) /* \_SB_.PCI0._OSC.CDW1 */ 690 Return (Arg3) 691 } 692 } // Method(_OSC) 693 694 // 695 // Device-Specific Methods 696 // 697 Method(_DSM, 0x4, NotSerialized) { 698 If (LEqual(Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) { 699 switch (ToInteger(Arg2)) { 700 // 701 // Function 0: Return supported functions 702 // 703 case(0) { 704 Return (Buffer() {0xFF}) 705 } 706 707 // 708 // Function 1: Return PCIe Slot Information 709 // 710 case(1) { 711 Return (Package(2) { 712 One, // Success 713 Package(3) { 714 0x1, // x1 PCIe link 715 0x1, // PCI express card slot 716 0x1 // WAKE# signal supported 717 } 718 }) 719 } 720 721 // 722 // Function 2: Return PCIe Slot Number. 723 // 724 case(2) { 725 Return (Package(1) { 726 Package(4) { 727 2, // Source ID 728 4, // Token ID: ID refers to a slot 729 0, // Start bit of the field to use. 730 7 // End bit of the field to use. 731 } 732 }) 733 } 734 735 // 736 // Function 3: Return Vendor-specific Token ID Strings. 737 // 738 case(3) { 739 Return (Package(0) {}) 740 } 741 742 // 743 // Function 4: Return PCI Bus Capabilities 744 // 745 case(4) { 746 Return (Package(2) { 747 One, // Success 748 Buffer() { 749 1,0, // Version 750 0,0, // Status, 0:Success 751 24,0,0,0, // Length 752 1,0, // PCI 753 16,0, // Length 754 0, // Attributes 755 0x0D, // Current Speed/Mode 756 0x3F,0, // Supported Speeds/Modes 757 0, // Voltage 758 0,0,0,0,0,0,0 // Reserved 759 } 760 }) 761 } 762 763 // 764 // Function 5: Return Ignore PCI Boot Configuration 765 // 766 case(5) { 767 Return (Package(1) {1}) 768 } 769 770 // 771 // Function 6: Return LTR Maximum Latency 772 // 773 case(6) { 774 Return (Package(4) { 775 Package(1){0}, // Maximum Snoop Latency Scale 776 Package(1){0}, // Maximum Snoop Latency Value 777 Package(1){0}, // Maximum No-Snoop Latency Scale 778 Package(1){0} // Maximum No-Snoop Latency Value 779 }) 780 } 781 782 // 783 // Function 7: Return PCI Express Naming 784 // 785 case(7) { 786 Return (Package(2) { 787 Package(1) {0}, 788 Package(1) {Unicode("PCI0")} 789 }) 790 } 791 792 // 793 // Not supported 794 // 795 default { 796 } 797 } 798 } 799 Return (Buffer(){0}) 800 } // Method(_DSM) 801 802 // 803 // Root-Complex 0 804 // 805 Device (RP0) 806 { 807 Name (_ADR, 0xF0000000) // _ADR: Bus 0, Dev 0, Func 0 808 } 809 } 810 } 811 } 812 813
