| /external/llvm/lib/Target/SystemZ/ |
| SystemZAsmPrinter.cpp | 34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg()))
48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
52 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
53 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg()))
61 .addReg(MI->getOperand(0).getReg())
62 .addReg(MI->getOperand(1).getReg())
63 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg()))
87 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| SystemZInstrBuilder.h | 62 return MIB.addReg(Reg).addImm(0).addReg(0);
67 return MIB.addImm(Offset).addReg(0);
77 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
85 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(0)
86 .addReg(Reg2, getKillRegState(isKill2));
92 MIB.addReg(AM.Base.Reg);
98 return MIB.addImm(AM.Disp).addReg(AM.IndexReg);
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86InstrBuilder.h | 94 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
100 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
110 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
119 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
128 MIB.addReg(AM.Base.Reg)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| AlphaLLRP.cpp | 78 .addReg(Alpha::R31)
79 .addReg(Alpha::R31);
90 .addReg(Alpha::R31)
91 .addReg(Alpha::R31);
93 .addReg(Alpha::R31)
94 .addReg(Alpha::R31);
104 .addReg(Alpha::R31).addReg(Alpha::R31);
106 .addReg(Alpha::R31).addReg(Alpha::R31)
[all...] |
| AlphaFrameLowering.cpp | 57 .addGlobalAddress(MF.getFunction()).addReg(Alpha::R27).addImm(++curgpdist);
59 .addGlobalAddress(MF.getFunction()).addReg(Alpha::R29).addImm(curgpdist);
83 .addReg(Alpha::R30);
86 .addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
88 .addImm(getLower16(NumBytes)).addReg(Alpha::R30);
96 .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
99 .addReg(Alpha::R30).addReg(Alpha::R30);
123 BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15
[all...] |
| AlphaInstrInfo.cpp | 103 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
106 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
113 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
116 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
127 .addReg(SrcReg)
128 .addReg(SrcReg, getKillRegState(KillSrc));
131 .addReg(SrcReg)
132 .addReg(SrcReg, getKillRegState(KillSrc));
135 .addReg(SrcReg)
136 .addReg(SrcReg, getKillRegState(KillSrc))
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| SparcFrameLowering.cpp | 56 .addReg(SP::O6).addImm(NumBytes);
64 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
66 .addReg(SP::O6).addReg(SP::G1);
78 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
79 .addReg(SP::G0);
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUFrameLowering.cpp | 125 .addReg(SPU::R1);
129 .addReg(SPU::R1);
131 BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
138 .addReg(SPU::R1);
142 .addReg(SPU::R2)
143 .addReg(SPU::R1);
145 .addReg(SPU::R1)
146 .addReg(SPU::R2);
148 .addReg(SPU::R2)
151 .addReg(SPU::R2
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 122 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
128 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
138 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
146 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
147 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
156 MIB.addReg(AM.Base.Reg)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 137 .addReg(SrcReg)
141 .addReg(SrcReg, RegState::Kill)
146 .addReg(SrcReg)
150 .addReg(SrcReg, RegState::Kill)
155 .addReg(SrcReg)
159 .addReg(SrcReg, RegState::Kill)
163 .addReg(DstReg, RegState::Kill)
317 .addReg(PPC::X31)
319 .addReg(PPC::X1);
323 .addReg(PPC::X0
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| Thumb2RegisterInfo.cpp | 49 .addReg(DestReg, getDefRegState(true), SubIdx)
50 .addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0)
|
| ARMExpandPseudoInsts.cpp | 425 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
426 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
428 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
430 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
461 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
498 MIB.addReg(D0).addReg(D1);
500 MIB.addReg(D2);
502 MIB.addReg(D3);
552 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| BlackfinInstrInfo.cpp | 106 .addReg(SrcReg, getKillRegState(KillSrc));
112 .addReg(SrcReg, getKillRegState(KillSrc))
120 .addReg(SrcReg, getKillRegState(KillSrc));
121 BuildMI(MBB, I, DL, get(BF::BITTGL), DestReg).addReg(DestReg).addImm(0);
126 .addReg(SrcReg, getKillRegState(KillSrc));
134 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(0);
139 .addReg(SrcReg, getKillRegState(KillSrc));
147 .addReg(SrcReg, getKillRegState(KillSrc));
153 .addReg(SrcReg, getKillRegState(KillSrc));
181 .addReg(SrcReg, getKillRegState(isKill)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMAsmPrinter.cpp | 162 .addReg(ThumbIndirectPads[i].first)
165 .addReg(0));
[all...] |
| ARMFrameLowering.cpp | 257 .addReg(Reg, RegState::Kill)
262 .addReg(Reg, RegState::Kill)
271 .addReg(Reg, RegState::Kill)
275 .addReg(Reg, RegState::Kill)
283 .addReg(Reg, RegState::Kill)
465 .addImm((unsigned)ARMCC::AL).addReg(0)
467 .addReg(ARM::R4, RegState::Implicit)
477 .addImm((unsigned)ARMCC::AL).addReg(0)
478 .addReg(ARM::R12, RegState::Kill)
479 .addReg(ARM::R4, RegState::Implicit
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmInstrumentation.cpp | 511 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(Reg));
516 EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(Reg));
547 MCInstBuilder(X86::MOV32rr).addReg(LocalFrameReg).addReg(FrameReg));
601 .addReg(X86::ESP)
602 .addReg(X86::ESP)
605 Out, MCInstBuilder(X86::PUSH32r).addReg(RegCtx.AddressReg(32)));
628 EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ShadowRegI32).addReg(
631 .addReg(ShadowRegI32
[all...] |
| /external/llvm/lib/CodeGen/GlobalISel/ |
| MachineIRBuilder.cpp | 82 .addReg(Res, RegState::Define)
83 .addReg(Op0)
84 .addReg(Op1);
91 MachineInstrBuilder(getMF(), NewMI).addReg(Res, RegState::Define).addReg(Op0);
|
| /external/llvm/lib/Target/Lanai/ |
| LanaiFrameLowering.cpp | 80 .addReg(Src)
115 .addReg(Lanai::FP)
116 .addReg(Lanai::SP)
124 .addReg(Lanai::SP)
132 .addReg(Lanai::SP)
188 .addReg(Lanai::FP)
193 .addReg(Lanai::FP)
|
| /external/llvm/lib/Target/AMDGPU/ |
| SILowerControlFlow.cpp | 237 .addReg(AMDGPU::VGPR0, RegState::Undef)
238 .addReg(AMDGPU::VGPR0, RegState::Undef)
239 .addReg(AMDGPU::VGPR0, RegState::Undef)
240 .addReg(AMDGPU::VGPR0, RegState::Undef);
255 .addReg(Vcc);
258 .addReg(AMDGPU::EXEC)
259 .addReg(Reg);
266 .addReg(Reg);
279 .addReg(Src); // Saved EXEC
286 .addReg(AMDGPU::EXEC
[all...] |
| SIFrameLowering.cpp | 108 .addReg(FlatScrInitHi, RegState::Kill);
115 .addReg(FlatScrInitLo)
116 .addReg(ScratchWaveOffsetReg);
120 .addReg(FlatScrInitLo, RegState::Kill)
218 .addReg(PreloadedScratchWaveOffsetReg, RegState::Kill);
236 .addReg(Lo, RegState::Kill);
238 .addReg(Hi, RegState::Kill);
249 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
253 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
257 .addReg(ScratchRsrcReg, RegState::ImplicitDefine)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 72 .addReg(FrameReg)
78 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
79 .addReg(FrameReg)
85 .addReg(FrameReg)
108 .addReg(FrameReg)
109 .addReg(ScratchOffset, RegState::Kill)
114 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
115 .addReg(FrameReg)
116 .addReg(ScratchOffset, RegState::Kill)
121 .addReg(FrameReg
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsLongBranch.cpp | 235 MIB.addReg(MO.getReg());
299 .addReg(Mips::SP).addImm(-8);
300 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
301 .addReg(Mips::SP).addImm(0);
324 .addReg(Mips::AT)
331 .addReg(Mips::RA).addReg(Mips::AT);
333 .addReg(Mips::SP).addImm(0);
338 .addReg(Mips::SP).addImm(8);
342 .addReg(Mips::ZERO).addReg(Mips::AT)
[all...] |
| MipsFastISel.cpp | 171 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
175 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
283 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
323 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
326 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
335 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
350 emitInst(Mips::MTC1, DestReg).addReg(TempReg);
358 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCAsmPrinter.cpp | 362 .addReg(ScratchReg)
366 .addReg(ScratchReg)
367 .addReg(ScratchReg)
371 .addReg(ScratchReg)
372 .addReg(ScratchReg)
376 .addReg(ScratchReg)
377 .addReg(ScratchReg)
383 .addReg(PPC::X2)
385 .addReg(PPC::X1));
395 .addReg(PPC::X2
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 240 .addReg(FrameReg)
241 .addReg(ScratchReg, RegState::Kill);
245 .addReg(Reg, getKillRegState(isKill))
246 .addReg(FrameReg)
247 .addReg(ScratchReg, RegState::Kill);
251 .addReg(FrameReg)
252 .addReg(ScratchReg, RegState::Kill);
261 .addReg(FrameReg)
266 .addReg(Reg, getKillRegState(isKill))
267 .addReg(FrameReg
[all...] |
