| /external/mesa3d/src/gallium/winsys/radeon/drm/ |
| radeon_drm_surface.c | 155 surf_drm->bankh = surf_ws->bankh;
196 surf_ws->bankh = surf_drm->bankh;
|
| radeon_drm_bo.c | 886 md->bankh = (args.tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
915 args.tiling_flags |= (md->bankh & RADEON_TILING_EG_BANKH_MASK) <<
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| radeon_video.c | 157 wh = surfaces[i]->bankw * surfaces[i]->bankh;
170 surfaces[i]->bankh = surfaces[best_tiling]->bankh;
|
| radeon_winsys.h | 239 unsigned bankh; member in struct:radeon_bo_metadata
311 * they will be treated as hints (e.g. bankw, bankh) and might be
324 unsigned bankh:4; /* max 8 */ member in struct:radeon_surf
|
| r600_texture.c | 293 metadata->bankh = surface->bankh;
600 fmask.bankh = rtex->surface.bankh;
605 fmask.bankh = 4;
642 out->bank_height = fmask.bankh;
912 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
914 rtex->surface.bankh, rtex->surface.num_banks, rtex->surface.mtilea,
920 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
[all...] |
| radeon_uvd.c | [all...] |
| /external/libdrm/radeon/ |
| radeon_surface.h | 124 * overridden (things lile bankw/bankh on evergreen for
131 uint32_t bankh; member in struct:radeon_surface
|
| radeon_surface.c | 679 mtileh = (tileh * surf->bankh * surf_man->hw_info.num_banks) / surf->mtilea;
773 switch (surf->bankh) {
783 if ((tileb * surf->bankh * surf->bankw) < surf_man->hw_info.group_bytes) {
908 /* compute best tile_split, bankw, bankh, mtilea
923 surf->bankh = 1;
926 for (; surf->bankh <= 8; surf->bankh *= 2) {
927 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) {
981 /* bankw or bankh greater than 1 increase alignment requirement, not
982 * sure if it's worth using smaller bankw & bankh to stick with 2
[all...] |
| /external/mesa3d/src/amd/vulkan/ |
| radv_radeon_winsys.h | 189 * they will be treated as hints (e.g. bankw, bankh) and might be
196 uint32_t bankh; member in struct:radeon_surf
239 unsigned bankh; member in struct:radeon_bo_metadata
|
| radv_image.c | 444 metadata->bankh = surface->bankh;
500 out->bank_height = fmask.bankh;
[all...] |
| radv_device.c | 1718 unsigned bankh = util_logbase2(iview->image->surface.bankh); local
[all...] |
| /external/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| radv_amdgpu_surface.c | 407 surf->bankw && surf->bankh && surf->mtilea && surf->tile_split) {
412 AddrTileInfoIn.bankHeight = surf->bankh;
474 surf->bankh = AddrSurfInfoOut.pTileInfo->bankHeight;
|
| radv_amdgpu_bo.c | 269 tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(md->bankh));
|
| /external/mesa3d/src/gallium/drivers/r600/ |
| evergreen_state.c | 670 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh; local
771 bankh = tmp->surface.bankh;
775 bankh = eg_bank_wh(bankh);
866 S_03001C_BANK_HEIGHT(bankh) |
997 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks; local
1173 unsigned macro_aspect, tile_split, bankh, bankw, nbanks; local
[all...] |
| /external/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| amdgpu_surface.c | 439 surf->bankw && surf->bankh && surf->mtilea && surf->tile_split) {
446 AddrTileInfoIn.bankHeight = surf->bankh;
515 surf->bankh = AddrSurfInfoOut.pTileInfo->bankHeight;
|
| amdgpu_bo.c | 621 md->bankh = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
649 tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(md->bankh));
|
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| si_state.c | 2188 unsigned bankh = util_logbase2(rtex->surface.bankh); local
[all...] |
