| /external/llvm/test/MC/AArch64/ |
| neon-scalar-cvt.s | 104 fcvtau h12, h13
105 fcvtau s12, s13
106 fcvtau d21, d14
108 // CHECK: fcvtau h12, h13 // encoding: [0xac,0xc9,0x79,0x7e]
109 // CHECK: fcvtau s12, s13 // encoding: [0xac,0xc9,0x21,0x7e]
110 // CHECK: fcvtau d21, d14 // encoding: [0xd5,0xc9,0x61,0x7e]
|
| neon-simd-misc.s | 658 fcvtau v4.4h, v0.4h
659 fcvtau v6.8h, v8.8h
660 fcvtau v6.4s, v8.4s
661 fcvtau v6.2d, v8.2d
662 fcvtau v4.2s, v0.2s
664 // CHECK: fcvtau v4.4h, v0.4h // encoding: [0x04,0xc8,0x79,0x2e]
665 // CHECK: fcvtau v6.8h, v8.8h // encoding: [0x06,0xc9,0x79,0x6e]
666 // CHECK: fcvtau v6.4s, v8.4s // encoding: [0x06,0xc9,0x21,0x6e]
667 // CHECK: fcvtau v6.2d, v8.2d // encoding: [0x06,0xc9,0x61,0x6e]
668 // CHECK: fcvtau v4.2s, v0.2s // encoding: [0x04,0xc8,0x21,0x2e
[all...] |
| fullfp16-neon-neg.s | 232 fcvtau h12, h13
366 fcvtau v4.4h, v0.4h
368 fcvtau v6.8h, v8.8h
|
| arm64-fp-encoding.s | 272 fcvtau w1, h2
273 fcvtau w1, s2
274 fcvtau w1, d2
275 fcvtau x1, h2
276 fcvtau x1, s2
277 fcvtau x1, d2
279 ; FP16: fcvtau w1, h2 ; encoding: [0x41,0x00,0xe5,0x1e]
281 ; NO-FP16-NEXT: fcvtau w1, h2
282 ; CHECK: fcvtau w1, s2 ; encoding: [0x41,0x00,0x25,0x1e]
283 ; CHECK: fcvtau w1, d2 ; encoding: [0x41,0x00,0x65,0x1e
[all...] |
| arm64-advsimd.s | [all...] |
| neon-diagnostics.s | [all...] |
| basic-a64-instructions.s | [all...] |
| /external/capstone/suite/MC/AArch64/ |
| neon-scalar-cvt.s.cs | 17 0xac,0xc9,0x21,0x7e = fcvtau s12, s13
18 0xd5,0xc9,0x61,0x7e = fcvtau d21, d14
|
| neon-simd-misc.s.cs | 192 0x06,0xc9,0x21,0x6e = fcvtau v6.4s, v8.4s
193 0x06,0xc9,0x61,0x6e = fcvtau v6.2d, v8.2d
194 0x04,0xc8,0x21,0x2e = fcvtau v4.2s, v0.2s
|
| basic-a64-instructions.s.cs | [all...] |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/ |
| advsimd-fp16.s | 108 tworeg_misc fcvtau
149 stworeg_misc fcvtau
|
| float-fp16.d | 130 [0-9a-f]+: 1e250001 fcvtau w1, s0
131 [0-9a-f]+: 9e650001 fcvtau x1, d0
132 [0-9a-f]+: 1ee50001 fcvtau w1, h0
133 [0-9a-f]+: 9ee50001 fcvtau x1, h0
|
| float-fp16.s | 122 .irp op, fcvtns, fcvtnu, fcvtau, fcvtas
|
| advsimd-fp16.d | 321 [0-9a-f]+: 6e61c820 fcvtau v0.2d, v1.2d
322 [0-9a-f]+: 2e21c820 fcvtau v0.2s, v1.2s
323 [0-9a-f]+: 6e21c820 fcvtau v0.4s, v1.4s
324 [0-9a-f]+: 2e79c820 fcvtau v0.4h, v1.4h
325 [0-9a-f]+: 6e79c820 fcvtau v0.8h, v1.8h
407 [0-9a-f]+: 7e61c820 fcvtau d0, d1
408 [0-9a-f]+: 7e21c820 fcvtau s0, s1
409 [0-9a-f]+: 7e79c820 fcvtau h0, h1
410 [0-9a-f]+: 7e79c800 fcvtau h0, h0
|
| fp_cvt_int.d | 30 58: 1e2500e7 fcvtau w7, s7
31 5c: 9e2500e7 fcvtau x7, s7
56 c0: 1e6500e7 fcvtau w7, d7
57 c4: 9e6500e7 fcvtau x7, d7
|
| neon-fp-cvt-int.d | 19 2c: 2e21c8e7 fcvtau v7.2s, v7.2s
31 5c: 6e21c8e7 fcvtau v7.4s, v7.4s
43 8c: 6e61c8e7 fcvtau v7.2d, v7.2d
55 bc: 7e21c8e7 fcvtau s7, s7
67 ec: 7e61c8e7 fcvtau d7, d7
[all...] |
| /external/vixl/test/aarch64/ |
| test-trace-aarch64.cc | 452 __ fcvtau(d14, d0);
453 __ fcvtau(s31, s14);
454 __ fcvtau(w16, d2);
455 __ fcvtau(w18, s0);
456 __ fcvtau(x26, d7);
457 __ fcvtau(x25, s19);
[all...] |
| test-simulator-aarch64.cc | [all...] |
| test-disasm-aarch64.cc | [all...] |
| /external/v8/src/arm64/ |
| macro-assembler-arm64-inl.h | 624 void MacroAssembler::Fcvtau(const Register& rd, const FPRegister& fn) {
627 fcvtau(rd, fn);
[all...] |
| assembler-arm64.h | [all...] |
| assembler-arm64.cc | 2059 void Assembler::fcvtau(const Register& rd, const FPRegister& fn) { function in class:v8::internal::Assembler
[all...] |
| /external/vixl/src/aarch64/ |
| assembler-aarch64.h | [all...] |
| macro-assembler-aarch64.h | [all...] |
| /external/valgrind/none/tests/arm64/ |
| fp_and_simd.stdout.exp | [all...] |
