| /external/llvm/test/MC/AArch64/ |
| armv8.1a-vhe.s | 7 msr TTBR1_EL2, x0
8 msr CONTEXTIDR_EL2, x0
9 msr CNTHV_TVAL_EL2, x0
10 msr CNTHV_CVAL_EL2, x0
11 msr CNTHV_CTL_EL2, x0
12 msr SCTLR_EL12, x0
13 msr CPACR_EL12, x0
14 msr TTBR0_EL12, x0
15 msr TTBR1_EL12, x0
16 msr TCR_EL12, x
[all...] |
| arm64-target-specific-sysreg.s | 7 msr CPM_IOACC_CTL_EL3, x0 label
10 // CHECK-CYCLONE: msr CPM_IOACC_CTL_EL3, x0 // encoding: [0x00,0xf2,0x1f,0xd5]
|
| armv8.2a-uao.s | 4 msr uao, #0
5 msr uao, #1
6 // CHECK: msr UAO, #0 // encoding: [0x7f,0x40,0x00,0xd5]
7 // CHECK: msr UAO, #1 // encoding: [0x7f,0x41,0x00,0xd5]
9 msr uao, #2
11 // CHECK-ERROR: msr uao, #2
14 msr uao, x1
16 // CHECK: msr UAO, x1 // encoding: [0x81,0x42,0x18,0xd5]
|
| trace-regs-diagnostics.s | 13 msr trcstatr, x0
14 msr trcidr8, x13
15 msr trcidr9, x25
16 msr trcidr10, x2
17 msr trcidr11, x19
18 msr trcidr12, x15
19 msr trcidr13, x24
20 msr trcidr0, x20
21 msr trcidr1, x5
22 msr trcidr2, x1
[all...] |
| armv8.1a-pan.s | 6 msr pan, #0
7 // CHECK: msr PAN, #0 // encoding: [0x9f,0x40,0x00,0xd5]
8 msr pan, #1
9 // CHECK: msr PAN, #1 // encoding: [0x9f,0x41,0x00,0xd5]
10 msr pan, x5
11 // CHECK: msr PAN, x5 // encoding: [0x65,0x42,0x18,0xd5]
15 msr pan, #-1
16 msr pan, #2
17 msr pan, w0
20 // CHECK-ERROR: msr pan, #-
[all...] |
| arm64-spsel-sysreg.s | 4 msr SPSel, #0 label
5 msr SPSel, x0 label
6 msr DAIFSet, #0 label
7 msr ESR_EL1, x0 label
11 // CHECK: msr SPSel, #0 // encoding: [0xbf,0x40,0x00,0xd5]
12 // CHECK: msr SPSel, x0 // encoding: [0x00,0x42,0x18,0xd5]
13 // CHECK: msr DAIFSet, #0 // encoding: [0xdf,0x40,0x03,0xd5]
14 // CHECK: msr ESR_EL1, x0 // encoding: [0x00,0x52,0x18,0xd5]
19 msr DAIFSet, x0 label
20 msr ESR_EL1, # label
[all...] |
| gicv3-regs.s | 116 msr icc_eoir1_el1, x27
117 msr icc_eoir0_el1, x5
118 msr icc_dir_el1, x13
119 msr icc_sgi1r_el1, x21
120 msr icc_asgi1r_el1, x25
121 msr icc_sgi0r_el1, x28
122 msr icc_bpr1_el1, x7
123 msr icc_bpr0_el1, x9
124 msr icc_pmr_el1, x29
125 msr icc_ctlr_el1, x2
[all...] |
| armv8.2a-statistical-profiling.s | 8 msr pmblimitr_el1, x0
9 msr pmbptr_el1, x0
10 msr pmbsr_el1, x0
11 msr pmbidr_el1, x0
12 msr pmscr_el2, x0
13 msr pmscr_el12, x0
14 msr pmscr_el1, x0
15 msr pmsicr_el1, x0
16 msr pmsirr_el1, x0
17 msr pmsfcr_el1, x
[all...] |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| msr-imm.s | 1 @ Check MSR and MRS instruction operand syntax.
2 @ Also check for MSR/MRS acceptance in ARM/THUMB modes.
9 msr APSR_nzcvq,#0xc0000004
10 msr APSR_g,#0xc0000004
11 msr APSR_nzcvq,#0xc0000004
12 msr APSR_nzcvqg,#0xc0000004
15 msr CPSR,#0xc0000004
16 msr CPSR_s,#0xc0000004
17 msr CPSR_f,#0xc0000004
18 msr CPSR_c,#0xc000000
[all...] |
| msr-reg.s | 1 @ Check MSR and MRS instruction operand syntax.
2 @ Also check for MSR/MRS acceptance in ARM/THUMB modes.
8 msr APSR,r9 @ deprecated usage.
9 msr APSR_g,r9
10 msr APSR_nzcvq,r9
11 msr APSR_nzcvqg,r9
14 msr CPSR,r9
15 msr CPSR_s,r9
16 msr CPSR_f,r9
17 msr CPSR_c,r
[all...] |
| msr-imm.d | 1 # name: MSR immediate operands
8 00000000 <[^>]*> e328f113 msr CPSR_f, #-1073741820 ; 0xc0000004
9 00000004 <[^>]*> e324f113 msr CPSR_s, #-1073741820 ; 0xc0000004
10 00000008 <[^>]*> e328f113 msr CPSR_f, #-1073741820 ; 0xc0000004
11 0000000c <[^>]*> e32cf113 msr CPSR_fs, #-1073741820 ; 0xc0000004
12 00000010 <[^>]*> e329f113 msr CPSR_fc, #-1073741820 ; 0xc0000004
13 00000014 <[^>]*> e324f113 msr CPSR_s, #-1073741820 ; 0xc0000004
14 00000018 <[^>]*> e328f113 msr CPSR_f, #-1073741820 ; 0xc0000004
15 0000001c <[^>]*> e321f113 msr CPSR_c, #-1073741820 ; 0xc0000004
16 00000020 <[^>]*> e322f113 msr CPSR_x, #-1073741820 ; 0xc000000
[all...] |
| msr-reg.d | 1 # name: MSR register operands
9 00000000 <[^>]*> e128f009 msr CPSR_f, r9
10 00000004 <[^>]*> e124f009 msr CPSR_s, r9
11 00000008 <[^>]*> e128f009 msr CPSR_f, r9
12 0000000c <[^>]*> e12cf009 msr CPSR_fs, r9
13 00000010 <[^>]*> e129f009 msr CPSR_fc, r9
14 00000014 <[^>]*> e124f009 msr CPSR_s, r9
15 00000018 <[^>]*> e128f009 msr CPSR_f, r9
16 0000001c <[^>]*> e121f009 msr CPSR_c, r9
17 00000020 <[^>]*> e122f009 msr CPSR_x, r
[all...] |
| mrs-msr-thumb-v7-m-bad.s | 7 msr apsr_nzcvqg, r4
8 msr iapsr_nzcvqg, r5
9 msr xpsr_nncvq, r6
10 msr xpsr_nzcv, r7
11 msr cpsr_f, r7
12 msr spsr, r8
13 msr primask_nzcvq, r9
|
| mrs-msr-arm-v6.s | 8 msr apsr_nzcvq, #0x40000000
9 msr cpsr_f, #0x20000000
10 msr spsr, #0x10000000
11 msr apsr_nzcvq, r4
12 msr cpsr_f, r5
13 msr spsr, r6
|
| mrs-msr-arm-v7-a.s | 8 msr apsr_nzcvqg, #0x40000000
9 msr cpsr_f, #0x20000000
10 msr spsr, #0x10000000
11 msr apsr_nzcvq, r4
12 msr cpsr_f, r5
13 msr spsr, r6
|
| arm6.s | 7 msr cpsr, r1
9 msr spsr_flg, r8
10 msr spsr_all, r9
15 msr CPSR, r1
17 msr SPSR_flg, r8
18 msr SPSR_all, r9
|
| archv8m-cmse-msr.s | 2 msr MSP, r0 label
3 msr MSP_NS, r0 label
4 msr PSP, r0 label
5 msr PSP_NS, r0 label
6 msr msp, r0 label
7 msr msp_ns, r0 label
8 msr psp, r0 label
9 msr psp_ns, r0 label
|
| mrs-msr-thumb-v7-m.s | 8 msr xpsr_nzcvq, r3
9 msr apsr_nzcvq, r4
10 msr iapsr_nzcvq, r5
11 msr primask, r6
|
| msr-reg-thumb.d | 1 # name: MSR register operands in thumb mode
3 # source: msr-reg.s
11 00000000 <[^>]*> f389 8800 msr CPSR_f, r9
12 00000004 <[^>]*> f389 8400 msr CPSR_s, r9
13 00000008 <[^>]*> f389 8800 msr CPSR_f, r9
14 0000000c <[^>]*> f389 8c00 msr CPSR_fs, r9
15 00000010 <[^>]*> f389 8900 msr CPSR_fc, r9
16 00000014 <[^>]*> f389 8400 msr CPSR_s, r9
17 00000018 <[^>]*> f389 8800 msr CPSR_f, r9
18 0000001c <[^>]*> f389 8100 msr CPSR_c, r
[all...] |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/ |
| msr.s | 22 msr daifset, #0
23 msr daifset, #1
24 msr daifset, #15
28 msr daifclr, #0
29 msr daifclr, #1
30 msr daifclr, #15
32 msr daif, x0
35 msr spsel, #0
36 msr spsel, #1
|
| uao.s | 28 msr uao, #1
29 msr uao, #0
31 msr uao, x0
|
| armv8_2-a-illegal.s | 2 /* MSR UAO, #imm4. */
4 msr uao, #\N
|
| deprecated.s | 5 msr spsr_hyp, x15
|
| msr.d | 8 0: d50340df msr daifset, #0x0
9 4: d50341df msr daifset, #0x1
10 8: d5034fdf msr daifset, #0xf
11 c: d50340ff msr daifclr, #0x0
12 10: d50341ff msr daifclr, #0x1
13 14: d5034fff msr daifclr, #0xf
14 18: d51b4220 msr daif, x0
16 20: d50040bf msr spsel, #0x0
17 24: d50041bf msr spsel, #0x1
|
| pan.s | 28 msr pan, #1
29 msr pan, #0
31 msr pan, x0
36 msr pan, #\N
|
