| /external/mesa3d/src/gallium/winsys/radeon/drm/ |
| radeon_drm_surface.c | 156 surf_drm->mtilea = surf_ws->mtilea;
197 surf_ws->mtilea = surf_drm->mtilea;
|
| radeon_drm_bo.c | 888 md->mtilea = (args.tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
922 args.tiling_flags |= (md->mtilea & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK) <<
[all...] |
| /external/libdrm/radeon/ |
| radeon_surface.h | 132 uint32_t mtilea; member in struct:radeon_surface
|
| radeon_surface.c | 678 mtilew = (tilew * surf->bankw * surf_man->hw_info.num_pipes) * surf->mtilea;
679 mtileh = (tileh * surf->bankh * surf_man->hw_info.num_banks) / surf->mtilea;
749 switch (surf->mtilea) {
759 if (surf_man->hw_info.num_banks < surf->mtilea) {
908 /* compute best tile_split, bankw, bankh, mtilea
924 surf->mtilea = surf_man->hw_info.num_banks;
931 if (surf->mtilea > 8) {
932 surf->mtilea = 8;
1023 surf->mtilea = 1 << (log2_int(h_over_w) >> 1);
[all...] |
| /external/mesa3d/src/amd/vulkan/ |
| radv_radeon_winsys.h | 197 uint32_t mtilea; member in struct:radeon_surf
241 unsigned mtilea; member in struct:radeon_bo_metadata
|
| radv_image.c | 446 metadata->mtilea = surface->mtilea;
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| radeon_video.c | 171 surfaces[i]->mtilea = surfaces[best_tiling]->mtilea;
|
| radeon_winsys.h | 241 unsigned mtilea; member in struct:radeon_bo_metadata
325 unsigned mtilea:4; /* max 8 */ member in struct:radeon_surf
|
| r600_texture.c | 295 metadata->mtilea = surface->mtilea;
601 fmask.mtilea = rtex->surface.mtilea;
912 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
914 rtex->surface.bankh, rtex->surface.num_banks, rtex->surface.mtilea,
[all...] |
| radeon_uvd.c | [all...] |
| /external/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| radv_amdgpu_surface.c | 407 surf->bankw && surf->bankh && surf->mtilea && surf->tile_split) {
413 AddrTileInfoIn.macroAspectRatio = surf->mtilea;
475 surf->mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio;
|
| radv_amdgpu_bo.c | 272 tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(md->mtilea));
|
| /external/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| amdgpu_surface.c | 439 surf->bankw && surf->bankh && surf->mtilea && surf->tile_split) {
447 AddrTileInfoIn.macroAspectRatio = surf->mtilea;
516 surf->mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio;
|
| amdgpu_bo.c | 623 md->mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
652 tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(md->mtilea));
|
| /external/mesa3d/src/gallium/drivers/r600/ |
| evergreen_state.c | 769 macro_aspect = tmp->surface.mtilea;
[all...] |
