| /external/capstone/arch/XCore/ |
| XCoreInstPrinter.c | 68 MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG;
69 MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id;
70 MI->flat_insn->detail->xcore.op_count++;
90 MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM;
91 MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)id;
92 MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG_INVALID;
93 MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0;
94 MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = 1;
109 MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = (uint8_t)id;
114 MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = atoi(p2)
[all...] |
| /bionic/libc/bionic/ |
| sys_sem.cpp | 60 int semop(int id, sembuf* ops, size_t op_count) {
61 return semtimedop(id, ops, op_count, nullptr);
64 int semtimedop(int id, sembuf* ops, size_t op_count, const timespec* ts) {
66 return syscall(SYS_semtimedop, id, ops, op_count, ts);
68 return syscall(SYS_ipc, SEMTIMEDOP, id, op_count, 0, ops, ts);
|
| /external/capstone/arch/SystemZ/ |
| SystemZInstPrinter.c | 63 MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM;
64 MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base);
65 MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.index = (uint8_t)SystemZ_map_register(Index);
66 MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = Disp;
67 MI->flat_insn->detail->sysz.op_count++;
71 MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
72 MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Disp;
73 MI->flat_insn->detail->sysz.op_count++;
88 MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_REG;
89 MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].reg = reg
[all...] |
| /external/capstone/cstool/ |
| cstool_mips.c | 21 if (mips->op_count)
22 printf("\top_count: %u\n", mips->op_count);
24 for (i = 0; i < mips->op_count; i++) {
|
| cstool_ppc.c | 49 if (ppc->op_count)
50 printf("\top_count: %u\n", ppc->op_count);
52 for (i = 0; i < ppc->op_count; i++) {
|
| cstool_sparc.c | 20 if (sparc->op_count)
21 printf("\top_count: %u\n", sparc->op_count);
23 for (i = 0; i < sparc->op_count; i++) {
|
| cstool_systemz.c | 20 if (sysz->op_count)
21 printf("\top_count: %u\n", sysz->op_count);
23 for (i = 0; i < sysz->op_count; i++) {
|
| cstool_xcore.c | 19 if (xcore->op_count)
20 printf("\top_count: %u\n", xcore->op_count);
22 for (i = 0; i < xcore->op_count; i++) {
|
| cstool_arm.c | 19 if (arm->op_count)
20 printf("\top_count: %u\n", arm->op_count);
22 for (i = 0; i < arm->op_count; i++) {
|
| /external/capstone/arch/AArch64/ |
| AArch64InstPrinter.c | 56 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_MEM;
57 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base = ARM64_REG_INVALID;
58 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index = ARM64_REG_INVALID;
59 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = 0;
62 MI->flat_insn->detail->arm64.op_count++;
119 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
120 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
121 MI->flat_insn->detail->arm64.op_count++;
122 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
123 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = getWRegFromXReg(MCOperand_getReg(Op1))
[all...] |
| /external/capstone/arch/ARM/ |
| ARMInstPrinter.c | 129 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM;
130 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_INVALID;
131 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID;
132 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1;
133 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0;
136 MI->flat_insn->detail->arm.op_count++;
143 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
144 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = v;
145 MI->flat_insn->detail->arm.op_count++;
189 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter)ShOpc
[all...] |
| /external/capstone/arch/PowerPC/ |
| PPCInstPrinter.c | 52 MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_MEM;
53 MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.base = PPC_REG_INVALID;
54 MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = 0;
57 MI->flat_insn->detail->ppc.op_count++;
118 ppc->operands[ppc->op_count].type = PPC_OP_IMM;
119 ppc->operands[ppc->op_count].imm = SH;
120 ++ppc->op_count;
363 MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
364 MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
365 MI->flat_insn->detail->ppc.op_count++
[all...] |
| /external/capstone/bindings/java/capstone/ |
| Mips.java | 60 public byte op_count; field in class:Mips.UnionOpInfo
68 readField("op_count");
69 op = new Operand[op_count];
70 if (op_count != 0)
76 return Arrays.asList("op_count", "op");
|
| Ppc.java | 71 public byte op_count; field in class:Ppc.UnionOpInfo
83 readField("op_count");
84 op = new Operand[op_count];
85 if (op_count != 0)
91 return Arrays.asList("bc", "bh", "update_cr0", "op_count", "op");
|
| Sparc.java | 57 public byte op_count; field in class:Sparc.UnionOpInfo
68 readField("op_count");
69 op = new Operand[op_count];
70 if (op_count != 0)
76 return Arrays.asList("cc", "hint", "op_count", "op");
|
| Systemz.java | 59 public byte op_count; field in class:Systemz.UnionOpInfo
69 readField("op_count");
70 op = new Operand[op_count];
71 if (op_count != 0)
77 return Arrays.asList("cc", "op_count", "op");
|
| Xcore.java | 56 public byte op_count; field in class:Xcore.UnionOpInfo
64 readField("op_count");
65 op = new Operand[op_count];
66 if (op_count != 0)
72 return Arrays.asList("op_count", "op");
|
| Arm64.java | 90 public byte op_count; field in class:Arm64.UnionOpInfo
102 readField("op_count");
103 op = new Operand[op_count];
104 if (op_count != 0)
110 return Arrays.asList("cc", "_update_flags", "_writeback", "op_count", "op");
|
| Arm.java | 92 public byte op_count; field in class:Arm.UnionOpInfo
110 readField("op_count");
111 op = new Operand[op_count];
112 if (op_count != 0)
119 "cps_mode", "cps_flag", "cc", "update_flags", "writeback", "mem_barrier", "op_count", "op");
|
| X86.java | 85 public byte op_count; field in class:X86.UnionOpInfo
98 "modrm", "sib", "disp", "sib_index", "sib_scale", "sib_base", "sse_cc", "avx_cc", "avx_sae", "avx_rm", "op_count", "op");
138 op = new Operand[e.op_count];
139 for (int i=0; i<e.op_count; i++)
|
| /external/capstone/arch/X86/ |
| X86ATTInstPrinter.c | 61 MI->flat_insn->detail->x86.op_count++;
273 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
274 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize;
275 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID;
276 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID;
277 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID;
278 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1;
279 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0;
289 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = reg;
307 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM
[all...] |
| X86IntelInstPrinter.c | 60 MI->flat_insn->detail->x86.op_count++;
299 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
300 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize;
301 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID;
302 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID;
303 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID;
304 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1;
305 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0;
315 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = reg;
330 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM
[all...] |
| /external/capstone/arch/Sparc/ |
| SparcInstPrinter.c | 56 MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG;
57 MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg;
58 MI->flat_insn->detail->sparc.op_count++;
70 MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_MEM;
71 MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = SPARC_REG_INVALID;
72 MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.disp = 0;
75 MI->flat_insn->detail->sparc.op_count++;
178 if (MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base)
179 MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.index = (uint8_t)reg;
181 MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = (uint8_t)reg
[all...] |
| /external/capstone/arch/Mips/ |
| MipsInstPrinter.c | 96 MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_MEM;
97 MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = MIPS_REG_INVALID;
98 MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = 0;
101 MI->flat_insn->detail->mips.op_count++;
198 MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = reg;
200 MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG;
201 MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg;
202 MI->flat_insn->detail->mips.op_count++;
222 MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = imm;
237 MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM
[all...] |
| /external/libunwind/tests/ |
| ia64-test-dyn1.c | 115 r_epi->op_count = 5;
121 assert ((unsigned) i <= r_epi->op_count);
126 r_pro->op_count = 4;
137 assert ((unsigned) i <= r_pro->op_count);
142 r->op_count = 16;
148 assert ((unsigned) i <= r->op_count);
153 r->op_count = 16;
161 assert ((unsigned) i <= r->op_count);
166 r->op_count = 16;
177 assert ((unsigned) i <= r->op_count);
[all...] |
