| /external/mesa3d/src/amd/vulkan/ |
| radv_cs.h | 46 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
47 radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2);
53 radeon_emit(cs, value);
60 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
61 radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2);
67 radeon_emit(cs, value);
77 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));
78 radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
79 radeon_emit(cs, value);
86 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0))
[all...] |
| radv_query.c | 253 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
254 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
255 radeon_emit(cs, avail_va);
256 radeon_emit(cs, avail_va >> 32);
257 radeon_emit(cs, 1); /* reference value */
258 radeon_emit(cs, 0xffffffff); /* mask */
259 radeon_emit(cs, 4); /* poll interval */
267 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
268 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
271 radeon_emit(cs, local_src_va)
[all...] |
| si_cmd_buffer.c | 179 radeon_emit(cs, 0);
180 radeon_emit(cs, 0);
181 radeon_emit(cs, 0);
184 radeon_emit(cs, 0);
186 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
187 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
193 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
195 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
222 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
223 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1))
[all...] |
| radv_cmd_buffer.c | 292 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
293 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
296 radeon_emit(cs, va);
297 radeon_emit(cs, va >> 32);
298 radeon_emit(cs, cmd_buffer->state.trace_id);
299 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
300 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
369 radeon_emit(cmd_buffer->cs, va);
370 radeon_emit(cmd_buffer->cs, va >> 32);
382 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0])
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| cayman_msaa.c | 167 radeon_emit(cs, cm_sample_locs_8x[0]);
168 radeon_emit(cs, cm_sample_locs_8x[4]);
169 radeon_emit(cs, 0);
170 radeon_emit(cs, 0);
171 radeon_emit(cs, cm_sample_locs_8x[1]);
172 radeon_emit(cs, cm_sample_locs_8x[5]);
173 radeon_emit(cs, 0);
174 radeon_emit(cs, 0);
175 radeon_emit(cs, cm_sample_locs_8x[2]);
176 radeon_emit(cs, cm_sample_locs_8x[6])
[all...] |
| r600_streamout.c | 174 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
175 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
177 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
178 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
179 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
180 radeon_emit(cs, 0);
181 radeon_emit(cs, S_008490_OFFSET_UPDATE_DONE(1)); /* reference value */
182 radeon_emit(cs, S_008490_OFFSET_UPDATE_DONE(1)); /* mask */
183 radeon_emit(cs, 4); /* poll interval */
206 radeon_emit(cs, (t[i]->b.buffer_offset
[all...] |
| r600_cs.h | 126 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
127 radeon_emit(cs, reloc);
135 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
136 radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2);
142 radeon_emit(cs, value);
149 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
150 radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2);
156 radeon_emit(cs, value);
165 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));
166 radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2 | (idx << 28))
[all...] |
| r600_viewport.c | 152 radeon_emit(cs, S_028250_TL_X(final.minx) |
155 radeon_emit(cs, S_028254_BR_X(final.maxx) |
207 radeon_emit(cs, fui(guardband_y)); /* R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
208 radeon_emit(cs, fui(1.0)); /* R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
209 radeon_emit(cs, fui(guardband_x)); /* R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
210 radeon_emit(cs, fui(1.0)); /* R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
288 radeon_emit(cs, fui(state->scale[0]));
289 radeon_emit(cs, fui(state->translate[0]));
290 radeon_emit(cs, fui(state->scale[1]));
291 radeon_emit(cs, fui(state->translate[1]))
[all...] |
| r600_query.c | 588 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
589 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
590 radeon_emit(cs, va);
591 radeon_emit(cs, (va >> 32) & 0xFFFF);
597 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
598 radeon_emit(cs, EVENT_TYPE(event_type_for_stream(query)) | EVENT_INDEX(3));
599 radeon_emit(cs, va);
600 radeon_emit(cs, (va >> 32) & 0xFFFF);
607 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
608 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2))
[all...] |
| r600_pipe_common.c | 115 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
116 radeon_emit(cs, op);
117 radeon_emit(cs, va);
118 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
119 radeon_emit(cs, old_fence); /* immediate data */
120 radeon_emit(cs, 0); /* unused */
123 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
124 radeon_emit(cs, op);
125 radeon_emit(cs, va);
126 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel))
[all...] |
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| cik_sdma.c | 57 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
60 radeon_emit(cs, csize);
61 radeon_emit(cs, 0); /* src/dst endian swap */
62 radeon_emit(cs, src_offset);
63 radeon_emit(cs, src_offset >> 32);
64 radeon_emit(cs, dst_offset);
65 radeon_emit(cs, dst_offset >> 32);
101 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_PACKET_CONSTANT_FILL, 0,
103 radeon_emit(cs, offset);
104 radeon_emit(cs, offset >> 32)
[all...] |
| si_state_draw.c | 201 radeon_emit(cs, ls->current->config.rsrc1);
202 radeon_emit(cs, ls_rsrc2);
231 radeon_emit(cs, offchip_layout);
232 radeon_emit(cs, tcs_out_offsets);
233 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
234 radeon_emit(cs, tcs_in_layout);
238 radeon_emit(cs, offchip_layout);
552 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
553 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
556 radeon_emit(cs, va); /* src address lo *
[all...] |
| si_perfcounter.c | 462 radeon_emit(cs, shaders & 0x7f);
463 radeon_emit(cs, 0xffffffff);
490 radeon_emit(cs, 0);
492 radeon_emit(cs, selectors[idx] | regs->select_or);
501 radeon_emit(cs, 0);
505 radeon_emit(cs, selectors[idx] | regs->select_or);
514 radeon_emit(cs, 0);
516 radeon_emit(cs, selectors[idx] | regs->select_or);
522 radeon_emit(cs, 0);
541 radeon_emit(cs, 0)
[all...] |
| si_compute.c | 226 radeon_emit(cs, 0);
227 radeon_emit(cs, 0);
228 radeon_emit(cs, 0);
232 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
233 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
239 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
241 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
263 radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
264 radeon_emit(cs, bc_va >> 40); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
386 radeon_emit(cs, shader_va >> 8)
[all...] |
| si_cp_dma.c | 80 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
81 radeon_emit(cs, header);
82 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
83 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
84 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
85 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
86 radeon_emit(cs, command);
90 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
91 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
92 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. *
[all...] |
| si_dma.c | 69 radeon_emit(cs, SI_DMA_PACKET(SI_DMA_PACKET_COPY, sub_cmd,
71 radeon_emit(cs, dst_offset);
72 radeon_emit(cs, src_offset);
73 radeon_emit(cs, (dst_offset >> 32UL) & 0xff);
74 radeon_emit(cs, (src_offset >> 32UL) & 0xff);
110 radeon_emit(cs, SI_DMA_PACKET(SI_DMA_PACKET_CONSTANT_FILL, 0,
112 radeon_emit(cs, offset);
113 radeon_emit(cs, clear_value);
114 radeon_emit(cs, (offset >> 32) << 16);
203 radeon_emit(cs, SI_DMA_PACKET(SI_DMA_PACKET_COPY, sub_cmd, size / 4))
[all...] |
| si_pm4.c | 153 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
154 radeon_emit(cs, ib->gpu_address);
155 radeon_emit(cs, (ib->gpu_address >> 32) & 0xffff);
156 radeon_emit(cs, (ib->b.b.width0 >> 2) & 0xfffff);
|
| si_descriptors.c | 147 radeon_emit(sctx->ce_ib, PKT3(PKT3_DUMP_CONST_RAM, 3, 0));
148 radeon_emit(sctx->ce_ib, ce_offset);
149 radeon_emit(sctx->ce_ib, size / 4);
150 radeon_emit(sctx->ce_ib, va);
151 radeon_emit(sctx->ce_ib, va >> 32);
174 radeon_emit(ib, PKT3(PKT3_LOAD_CONST_RAM, 3, 0));
175 radeon_emit(ib, va);
176 radeon_emit(ib, va >> 32);
177 radeon_emit(ib, list_size / 4);
178 radeon_emit(ib, desc->ce_offset)
[all...] |
| si_state.c | 250 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
251 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
252 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
943 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
947 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
[all...] |
| /external/mesa3d/src/gallium/drivers/r600/ |
| evergreen_hw_context.c | 71 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, sub_cmd, csize));
72 radeon_emit(cs, dst_offset & 0xffffffff);
73 radeon_emit(cs, src_offset & 0xffffffff);
74 radeon_emit(cs, (dst_offset >> 32UL) & 0xff);
75 radeon_emit(cs, (src_offset >> 32UL) & 0xff);
131 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
132 radeon_emit(cs, clear_value); /* DATA [31:0] */
133 radeon_emit(cs, sync | PKT3_CP_DMA_SRC_SEL(2)); /* CP_SYNC [31] | SRC_SEL[30:29] */
134 radeon_emit(cs, offset); /* DST_ADDR_LO [31:0] */
135 radeon_emit(cs, (offset >> 32) & 0xff); /* DST_ADDR_HI [7:0] *
[all...] |
| r600_hw_context.c | 122 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
123 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
136 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
137 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
142 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
143 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
156 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
157 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
230 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
231 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL *
[all...] |
| evergreen_compute.c | 415 radeon_emit(cs, 0); /* R_00899C_VGT_COMPUTE_START_X */
416 radeon_emit(cs, 0); /* R_0089A0_VGT_COMPUTE_START_Y */
417 radeon_emit(cs, 0); /* R_0089A4_VGT_COMPUTE_START_Z */
423 radeon_emit(cs, info->block[0]); /* R_0286EC_SPI_COMPUTE_NUM_THREAD_X */
424 radeon_emit(cs, info->block[1]); /* R_0286F0_SPI_COMPUTE_NUM_THREAD_Y */
425 radeon_emit(cs, info->block[2]); /* R_0286F4_SPI_COMPUTE_NUM_THREAD_Z */
439 radeon_emit(cs, PKT3C(PKT3_DISPATCH_DIRECT, 3, 0));
440 radeon_emit(cs, info->grid[0]);
441 radeon_emit(cs, info->grid[1]);
442 radeon_emit(cs, info->grid[2])
[all...] |
| evergreen_state.c | 889 radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs));
890 radeon_emit(cs, 0);
891 radeon_emit(cs, 0);
893 radeon_emit(cs, a->sq_gpr_resource_mgmt_1);
894 radeon_emit(cs, a->sq_gpr_resource_mgmt_2);
895 radeon_emit(cs, a->sq_gpr_resource_mgmt_3);
[all...] |
| r600_state.c | 275 radeon_emit(cs, fui(offset_scale));
276 radeon_emit(cs, fui(offset_units));
277 radeon_emit(cs, fui(offset_scale));
278 radeon_emit(cs, fui(offset_units));
[all...] |
| r600_state_common.c | 220 radeon_emit(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
221 radeon_emit(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
222 radeon_emit(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
223 radeon_emit(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
233 radeon_emit(cs, a->vgt_indx_offset); /* R_028408_VGT_INDX_OFFSET */
234 radeon_emit(cs, a->vgt_multi_prim_ib_reset_indx); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
266 radeon_emit(cs, /* R_028430_DB_STENCILREFMASK */
270 radeon_emit(cs, /* R_028434_DB_STENCILREFMASK_BF */
[all...] |
