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    Searched refs:reset_req (Results 1 - 2 of 2) sorted by null

  /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/
PcieInitLib.c 664 u_sc_pcie_hilink_pcs_reset_req reset_req; local
669 reset_req.UInt32 = 0;
670 reset_req.UInt32 = reset_req.UInt32 | (0x1 << PortIndexInSicl);
671 RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG, reset_req.UInt32);
672 RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_APB_RESET_REQ_REG, reset_req.UInt32);
674 reset_req.UInt32 = 0;
675 reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * PortIndexInSicl));
676 RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG, reset_req.UInt32);
700 u_sc_pcie_hilink_pcs_reset_req reset_req; local
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  /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/
PcieInitLib.c 543 u_sc_pcie_hilink_pcs_reset_req reset_req; local
550 reset_req.UInt32 = 0;
551 reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port);
552 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG, reset_req.UInt32);
554 reset_req.UInt32 = 0;
555 reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port));
556 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG, reset_req.UInt32);
591 u_sc_pcie_hilink_pcs_reset_req reset_req; local
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