| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| thumbv6.s | 10 rev16 r5, r1
|
| thumbv6.d | 12 0+008 <[^>]*> ba4d * rev16 r5, r1
|
| thumb2_bad_reg.s | 366 @ REV16
367 rev16.w r13, r0
368 rev16.w r15, r0
369 rev16.w r0, r13
370 rev16.w r0, r15
|
| archv6.s | 33 rev16 r2, r4
|
| t16-bad.l | 21 [^:]*:41: Error: lo register required -- `rev16 r8,r0'
22 [^:]*:41: Error: lo register required -- `rev16 r0,r8'
|
| thumb32.d | [all...] |
| archv6.d | 36 0+070 <[^>]*> e6bf2fb4 ? rev16 r2, r4
|
| thumb32.s | 598 rx rev16 rev16.w
|
| thumb2_bad_reg.l | 281 [^:]*:[0-9]+: Error: r13 not allowed here -- `rev16.w r13,r0'
282 [^:]*:[0-9]+: Error: r15 not allowed here -- `rev16.w r15,r0'
283 [^:]*:[0-9]+: Error: r13 not allowed here -- `rev16.w r0,r13'
284 [^:]*:[0-9]+: Error: r15 not allowed here -- `rev16.w r0,r15'
[all...] |
| /external/capstone/suite/MC/ARM/ |
| thumb.s.cs | 8 0x63,0xba = rev16 r3, r4
|
| basic-thumb-instructions.s.cs | 92 0x57,0xba = rev16 r7, r2
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/ |
| alias-2.s | 41 .irp op, rev, rev16, rev64
|
| alias-2.d | 103 [0-9a-f]+: dac007e0 rev16 x0, xzr
104 [0-9a-f]+: dac00420 rev16 x0, x1
105 [0-9a-f]+: dac0043f rev16 xzr, x1
106 [0-9a-f]+: dac007ff rev16 xzr, xzr
|
| verbose-error.s | 28 rev16 v10.2s, v11.2s
|
| verbose-error.l | 82 [^:]*:28: Error: operand mismatch -- `rev16 v10.2s,v11.2s'
84 [^:]*:28: Info: rev16 v10.8b,v11.8b
86 [^:]*:28: Info: rev16 v10.16b,v11.16b
|
| /external/llvm/test/MC/ARM/ |
| thumb.s | 19 rev16 r3, r4
22 @ CHECK: rev16 r3, r4 @ encoding: [0x63,0xba]
|
| basic-thumb-instructions.s | 472 @ REV/REV16/REVSH
475 rev16 r7, r2
479 @ CHECK: rev16 r7, r2 @ encoding: [0x57,0xba]
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| thumb.s | 19 rev16 r3, r4
22 @ CHECK: rev16 r3, r4 @ encoding: [0x63,0xba]
|
| basic-thumb-instructions.s | 421 @ REV/REV16/REVSH
424 rev16 r7, r2
428 @ CHECK: rev16 r7, r2 @ encoding: [0x57,0xba]
|
| /device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/ |
| core_cmInstr.h | 131 rev16 r0, r0
491 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
| /external/llvm/test/MC/AArch64/ |
| neon-simd-misc.s | 33 rev16 v30.16b, v31.16b
34 rev16 v21.8b, v1.8b
36 // CHECK: rev16 v30.16b, v31.16b // encoding: [0xfe,0x1b,0x20,0x4e]
37 // CHECK: rev16 v21.8b, v1.8b // encoding: [0x35,0x18,0x20,0x0e]
[all...] |
| arm64-arithmetic-encoding.s | 440 rev16 w1, w2
441 rev16 x1, x2
|
| /external/capstone/suite/MC/AArch64/ |
| neon-simd-misc.s.cs | 12 0xfe,0x1b,0x20,0x4e = rev16 v30.16b, v31.16b
13 0x35,0x18,0x20,0x0e = rev16 v21.8b, v1.8b
|
| /external/valgrind/none/tests/arm/ |
| v6intARM.stdout.exp | [all...] |
| /external/vixl/test/aarch32/ |
| test-assembler-cond-rd-rn-t32.cc | 55 M(rev16) \
332 #include "aarch32/traces/assembler-cond-rd-rn-rev16-t32.h"
|
