| /external/capstone/suite/MC/ARM/ |
| arm-shift-encoding.s.cs | 9 0x60,0x00,0x90,0xe7 = ldr r0, [r0, r0, rrx]
18 0x60,0xf0,0xd0,0xf7 = pld [r0, r0, rrx]
27 0x60,0x00,0x80,0xe7 = str r0, [r0, r0, rrx]
29 0x62,0x00,0x91,0xe6 = ldr r0, [r1], r2, rrx
40 0x6c,0x70,0xa2,0xe0 = adc r7, r2, r12, rrx
49 0x62,0x00,0x57,0xe1 = cmp r7, r2, rrx
|
| thumb-shift-encoding.s.cs | 9 0x62,0xeb,0x3c,0x07 = sbc.w r7, r2, r12, rrx
18 0x02,0xea,0x3c,0x07 = and.w r7, r2, r12, rrx
|
| basic-arm-instructions.s.cs | 29 0x66,0x40,0xa5,0xe0 = adc r4, r5, r6, rrx
41 0x65,0x40,0xa4,0xe0 = adc r4, r4, r5, rrx
46 0x65,0x40,0xa4,0xe0 = adc r4, r4, r5, rrx
59 0x66,0x40,0x85,0xe0 = add r4, r5, r6, rrx
71 0x65,0x40,0x84,0xe0 = add r4, r4, r5, rrx
87 0x66,0xa0,0x01,0xe0 = and r10, r1, r6, rrx
100 0x61,0xa0,0x0a,0xe0 = and r10, r10, r1, rrx
122 0x66,0xa0,0xc1,0xe1 = bic r10, r1, r6, rrx
134 0x61,0xa0,0xca,0xe1 = bic r10, r10, r1, rrx
166 0x66,0x00,0x71,0xe1 = cmn r1, r6, rrx
[all...] |
| /external/llvm/test/MC/ARM/ |
| arm-shift-encoding.s | 10 ldr r0, [r0, r0, rrx]
20 @ CHECK: ldr r0, [r0, r0, rrx] @ encoding: [0x60,0x00,0x90,0xe7]
30 pld [r0, r0, rrx]
40 @ CHECK: [r0, r0, rrx] @ encoding: [0x60,0xf0,0xd0,0xf7]
50 str r0, [r0, r0, rrx]
60 @ CHECK: str r0, [r0, r0, rrx] @ encoding: [0x60,0x00,0x80,0xe7]
68 ldr r0, [r1], r2, rrx
73 @ CHECK: ldr r0, [r1], r2, rrx @ encoding: [0x62,0x00,0x91,0xe6]
88 adc r7, r2, r12, rrx
98 @ CHECK: adc r7, r2, r12, rrx @ encoding: [0x6c,0x70,0xa2,0xe0
[all...] |
| thumb-shift-encoding.s | 14 sbc.w r7, r2, r12, rrx
24 @ CHECK: sbc.w r7, r2, r12, rrx @ encoding: [0x62,0xeb,0x3c,0x07]
34 and.w r7, r2, r12, rrx
44 @ CHECK: and.w r7, r2, r12, rrx @ encoding: [0x02,0xea,0x3c,0x07]
|
| basic-arm-instructions.s | 86 adc r4, r5, r6, rrx
100 adc r4, r5, rrx
105 adc r4, r5, rrx
124 @ CHECK: adc r4, r5, r6, rrx @ encoding: [0x66,0x40,0xa5,0xe0]
137 @ CHECK: adc r4, r4, r5, rrx @ encoding: [0x65,0x40,0xa4,0xe0]
142 @ CHECK: adc r4, r4, r5, rrx @ encoding: [0x65,0x40,0xa4,0xe0]
205 add r4, r5, r6, rrx
229 add r4, r5, rrx
261 @ CHECK: add r4, r5, r6, rrx @ encoding: [0x66,0x40,0x85,0xe0]
284 @ CHECK: add r4, r4, r5, rrx @ encoding: [0x65,0x40,0x84,0xe0
[all...] |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| tcompat.s | 47 rrx r0,r9
|
| tcompat.d | 51 0+a0 <[^>]*> e1a00069 ? rrx r0, r9
|
| inst.d | 18 0+018 <[^>]*> e1a0e06f ? rrx lr, pc
187 0+2ac <[^>]*> e1a01062 ? rrx r1, r2
203 0+2ec <[^>]*> e1a01062 ? rrx r1, r2
|
| wince_inst.d | 20 0+018 <[^>]*> e1a0e06f ? rrx lr, pc
189 0+2ac <[^>]*> e1a01062 ? rrx r1, r2
205 0+2ec <[^>]*> e1a01062 ? rrx r1, r2
|
| inst.s | 11 mov r14, r15, rrx
206 mov r1, r2, rrx
222 mov r1, r2, RRX
|
| thumb32.s | 104 add.w r8, r9, r10, rrx
632 rrx: label
633 rrx r1, r2
|
| thumb2_bad_reg.s | 391 @ RRX
392 rrx r13, r0
393 rrx r15, r0
394 rrx r0, r13
395 rrx r0, r15
|
| /prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/arm/armasm/ |
| gnu.go | 89 X += ", rrx"
155 return gnuArg(inst, -1, arg.Reg) + ", rrx"
|
| /prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/arm/armasm/ |
| gnu.go | 89 X += ", rrx"
155 return gnuArg(inst, -1, arg.Reg) + ", rrx"
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
| ARMAddressingModes.h | 32 rrx enumerator in enum:llvm::ARM_AM::ShiftOpc
51 case ARM_AM::rrx: return "rrx";
104 // reg [asr|lsl|lsr|ror|rrx] reg
105 // reg [asr|lsl|lsr|ror|rrx] imm
|
| ARMMCCodeEmitter.cpp | 186 case ARM_AM::rrx: return 3;
[all...] |
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| basic-arm-instructions.s | 66 adc r4, r5, r6, rrx
80 adc r4, r5, rrx
85 adc r4, r5, rrx
104 @ CHECK: adc r4, r5, r6, rrx @ encoding: [0x66,0x40,0xa5,0xe0]
117 @ CHECK: adc r4, r4, r5, rrx @ encoding: [0x65,0x40,0xa4,0xe0]
122 @ CHECK: adc r4, r4, r5, rrx @ encoding: [0x65,0x40,0xa4,0xe0]
159 add r4, r5, r6, rrx
173 add r4, r5, rrx
186 @ CHECK: add r4, r5, r6, rrx @ encoding: [0x66,0x40,0x85,0xe0]
200 @ CHECK: add r4, r4, r5, rrx @ encoding: [0x65,0x40,0x84,0xe0
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAddressingModes.h | 33 rrx enumerator in enum:llvm::ARM_AM::ShiftOpc
52 case ARM_AM::rrx: return "rrx";
105 // reg [asr|lsl|lsr|ror|rrx] reg
106 // reg [asr|lsl|lsr|ror|rrx] imm
|
| ARMMCCodeEmitter.cpp | 212 case ARM_AM::rrx: return 3;
[all...] |
| /device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/ |
| core_cmInstr.h | 302 rrx r0, r0
745 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 91 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
251 if (ShOpc == ARM_AM::rrx)
268 if (ShOpc == ARM_AM::rrx)
832 if (ShOpc != ARM_AM::rrx)
|
| /frameworks/av/media/libstagefright/codecs/m4v_h263/enc/src/ |
| sad_inline.h | 217 ANDS x7, mask, x7, rrx; local
401 "ands %1, %4, %1,rrx\n\t"
|
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 53 if (ShOpc != ARM_AM::rrx) {
116 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
354 if (ShOpc == ARM_AM::rrx)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMCodeEmitter.cpp | 407 case ARM_AM::rrx: return 3;
808 case ARM::RRX:
809 // rrx
[all...] |
