| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/sparc/ |
| imm-plus-rreg.s | 0 ! simm13 + regrs1 address using r<0..31> instead of [goli]<0..7>
|
| imm-plus-rreg.d | 3 #name: address: simm13 + rreg
|
| /external/capstone/arch/Sparc/ |
| SparcDisassembler.c | 260 unsigned simm13 = 0; local
263 simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
280 MCOperand_CreateImm0(MI, simm13);
381 unsigned simm13 = 0; local
384 simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
398 // Decode RS1 | SIMM13.
400 MCOperand_CreateImm0(MI, simm13);
417 unsigned simm13 = 0; local
419 simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
428 // Decode RS2 | SIMM13
448 unsigned simm13 = 0; local
[all...] |
| /external/llvm/lib/Target/Sparc/Disassembler/ |
| SparcDisassembler.cpp | 387 unsigned simm13 = 0; local
389 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
407 MI.addOperand(MCOperand::createImm(simm13));
542 unsigned simm13 = 0; local
544 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
558 // Decode RS1 | SIMM13.
560 MI.addOperand(MCOperand::createImm(simm13));
575 unsigned simm13 = 0; local
577 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
586 // Decode RS2 | SIMM13
606 unsigned simm13 = 0; local
[all...] |
| /external/valgrind/VEX/priv/ |
| host_arm_defs.h | 140 Int simm13; /* -4095 .. +4095 */ member in struct:__anon41591::__anon41592::__anon41593
151 extern ARMAMode1* ARMAMode1_RI ( HReg reg, Int simm13 );
[all...] |
| host_arm_defs.c | 205 ARMAMode1* ARMAMode1_RI ( HReg reg, Int simm13 ) {
209 am->ARMam1.RI.simm13 = simm13;
210 vassert(-4095 <= simm13 && simm13 <= 4095);
226 vex_printf("%d(", am->ARMam1.RI.simm13);
[all...] |
| host_arm_isel.c | 886 && am->ARMam1.RI.simm13 >= -4095
887 && am->ARMam1.RI.simm13 <= 4095 );
915 /* {Add32,Sub32}(expr,simm13) */
[all...] |
