/external/mesa3d/src/gallium/drivers/radeonsi/ |
si_dma.c | 147 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size; local 170 slice_tile_max = (rtiled->surface.level[tiled_lvl].nblk_x * 209 radeon_emit(cs, (slice_tile_max << 0) | (pipe_config << 26));
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cik_sdma.c | 280 unsigned slice_tile_max = tiled_slice_pitch / 64 - 1; local 384 slice_tile_max < (1 << 22) && 402 radeon_emit(cs, slice_tile_max);
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si_state.c | 2511 unsigned pitch_tile_max, slice_tile_max, tile_mode_index; local [all...] |
/external/mesa3d/src/amd/vulkan/ |
radv_image.c | 494 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64; 495 if (out->slice_tile_max) 496 out->slice_tile_max -= 1; 556 out->slice_tile_max = (width * height) / (128*128); 557 if (out->slice_tile_max) 558 out->slice_tile_max -= 1; [all...] |
radv_device.c | 1588 unsigned pitch_tile_max, slice_tile_max, tile_mode_index; local [all...] |
radv_private.h | 985 unsigned slice_tile_max; member in struct:radv_fmask_info 993 unsigned slice_tile_max; member in struct:radv_cmask_info [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
r600_texture.c | 636 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64; 637 if (out->slice_tile_max) 638 out->slice_tile_max -= 1; 685 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1; 730 out->slice_tile_max = (width * height) / (128*128); 731 if (out->slice_tile_max) 732 out->slice_tile_max -= 1; 920 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n", 923 rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index); 927 "slice_tile_max=%u\n" [all...] |
r600_pipe_common.h | 228 unsigned slice_tile_max; member in struct:r600_fmask_info 236 unsigned slice_tile_max; member in struct:r600_cmask_info [all...] |
/external/mesa3d/src/gallium/drivers/r600/ |
r600_state.c | 2823 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size; local [all...] |
evergreen_state.c | 3355 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size; local [all...] |