/art/runtime/interpreter/mterp/x86/ |
fpcvt.S | 8 $load VREG_ADDRESS(rINST) # %st0 <- vB 11 $store VREG_ADDRESS(%ecx) # vA <- %st0
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op_rem_double.S | 5 fldl VREG_ADDRESS(%eax) # %st0 <- fp[vCC]
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cvtfp_int.S | 13 fldl VREG_ADDRESS(rINST) # %st0 <- vB 15 flds VREG_ADDRESS(rINST) # %st0 <- vB
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/external/valgrind/coregrind/ |
m_stacks.c | 117 Stack *st0, *st1, *st2; local 121 st0 = stacks; 125 if (st0 == NULL || st0 == st) break; 127 st1 = st0; 128 st0 = st0->next; 130 vg_assert(st0 == st); 131 if (st0 != NULL && st1 != NULL && st2 != NULL) { 133 /* st0 points to st, st1 to its predecessor, and st2 to st1' [all...] |
/art/runtime/interpreter/mterp/x86_64/ |
op_rem_double.S | 5 fldl VREG_ADDRESS(%rax) # %st0 <- fp[vCC]
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/external/valgrind/none/tests/amd64/ |
x87trigOOR.c | 15 typedef struct { Double arg; Double st0; Double st1; UShort fpusw; } Res; member in struct:__anon43000 28 assert(my_offsetof(Res,st0) == 8); 39 "fstpl 8(%0)" "\n\t" // .st0 50 assert(my_offsetof(Res,st0) == 8); 61 "fstpl 8(%0)" "\n\t" // .st0 72 assert(my_offsetof(Res,st0) == 8); 83 "fstpl 8(%0)" "\n\t" // .st0 94 assert(my_offsetof(Res,st0) == 8); 105 "fstpl 8(%0)" "\n\t" // .st0 121 name, r.arg, r.st0, r.st1, (UInt)r.fpusw) [all...] |
gen_insn_test.pl | 64 st0 => 0, st1 => 1, st2 => 2, st3 => 3,
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/external/valgrind/none/tests/x86/ |
x87trigOOR.c | 15 typedef struct { Double arg; Double st0; Double st1; UShort fpusw; } Res; member in struct:__anon43149 28 assert(my_offsetof(Res,st0) == 8); 39 "fstpl 8(%0)" "\n\t" // .st0 50 assert(my_offsetof(Res,st0) == 8); 61 "fstpl 8(%0)" "\n\t" // .st0 72 assert(my_offsetof(Res,st0) == 8); 83 "fstpl 8(%0)" "\n\t" // .st0 94 assert(my_offsetof(Res,st0) == 8); 105 "fstpl 8(%0)" "\n\t" // .st0 121 name, r.arg, r.st0, r.st1, (UInt)r.fpusw) [all...] |
gen_insn_test.pl | 59 st0 => 0, st1 => 1, st2 => 2, st3 => 3,
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/external/libvpx/libvpx/vpx_dsp/mips/ |
convolve2_avg_horiz_dspr2.c | 122 uint32_t st0, st1; local 158 "lbux %[st0], %[Temp1](%[cm]) \n\t" 165 "addqh_r.w %[Temp2], %[Temp2], %[st0] \n\t" 179 "lbux %[st0], %[Temp1](%[cm]) \n\t" 181 "addqh_r.w %[Temp2], %[Temp2], %[st0] \n\t" 204 "lbux %[st0], %[Temp3](%[cm]) \n\t" 210 "addqh_r.w %[tp1], %[tp1], %[st0] \n\t" 244 [tp4] "=&r"(tp4), [st0] "=&r"(st0), [st1] "=&r"(st1), [p1] "=&r"(p1), [all...] |
convolve2_horiz_dspr2.c | 107 uint32_t st0, st1; local 141 "lbux %[st0], %[Temp1](%[cm]) \n\t" 152 "sb %[st0], 0(%[dst]) \n\t" 161 "lbux %[st0], %[Temp1](%[cm]) \n\t" 171 "sb %[st0], 4(%[dst]) \n\t" 180 "lbux %[st0], %[Temp3](%[cm]) \n\t" 191 "sb %[st0], 6(%[dst]) \n\t" 206 [st0] "=&r"(st0), [st1] "=&r"(st1), [p1] "=&r"(p1), [p2] "=&r"(p2), [all...] |
convolve8_avg_horiz_dspr2.c | 149 uint32_t st0, st1; local 195 "lbux %[st0], %[Temp1](%[cm]) \n\t" 206 "addqh_r.w %[Temp2], %[Temp2], %[st0] \n\t" 222 "lbux %[st0], %[Temp1](%[cm]) \n\t" 224 "addqh_r.w %[Temp2], %[Temp2], %[st0] \n\t" 255 "lbux %[st0], %[Temp3](%[cm]) \n\t" 264 "addqh_r.w %[tp1], %[tp1], %[st0] \n\t" 305 [tn2] "=&r"(tn2), [tn3] "=&r"(tn3), [st0] "=&r"(st0), [all...] |
convolve8_horiz_dspr2.c | 138 uint32_t st0, st1; local 182 "lbux %[st0], %[Temp1](%[cm]) \n\t" 197 "sb %[st0], 0(%[dst]) \n\t" 211 "lbux %[st0], %[Temp1](%[cm]) \n\t" 221 "sb %[st0], 4(%[dst]) \n\t" 235 "lbux %[st0], %[Temp3](%[cm]) \n\t" 253 "sb %[st0], 6(%[dst]) \n\t" 271 [tn2] "=&r"(tn2), [tn3] "=&r"(tn3), [st0] "=&r"(st0), [all...] |
/prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/x86/x86asm/ |
xed_test.go | 144 // DD C9, DF C9: xed says 'fxch st0, st1' but that instruction is D9 C9. 149 // DC D4: xed says 'fcom st0, st4' but that instruction is D8 D4. 154 // DE D4: xed says 'fcomp st0, st4' but that instruction is D8 D4. 159 // DF D4: xed says 'fstp st4, st0' but that instruction is DD D4.
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intel.go | 293 args = append(args, "st0") 298 args = []string{"st0", "st1"} 303 args = append(args, "st0") 308 args = []string{"st0", args[0]} 513 F0: "st0",
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/prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/x86/x86asm/ |
xed_test.go | 144 // DD C9, DF C9: xed says 'fxch st0, st1' but that instruction is D9 C9. 149 // DC D4: xed says 'fcom st0, st4' but that instruction is D8 D4. 154 // DE D4: xed says 'fcomp st0, st4' but that instruction is D8 D4. 159 // DF D4: xed says 'fstp st4, st0' but that instruction is DD D4.
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intel.go | 293 args = append(args, "st0") 298 args = []string{"st0", "st1"} 303 args = append(args, "st0") 308 args = []string{"st0", args[0]} 513 F0: "st0",
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/device/linaro/bootloader/edk2/BaseTools/Source/C/VfrCompile/Pccts/dlg/ |
dlg_a.c | 563 static DfaState st0[42] = {
variable 1233 st0,
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/art/runtime/interpreter/mterp/out/ |
mterp_x86.S | [all...] |
mterp_x86_64.S | [all...] |
/device/linaro/bootloader/edk2/BaseTools/Source/C/VfrCompile/Pccts/antlr/ |
scan.c | 1871 static DfaState st0[60] = { variable [all...] |
/external/elfutils/tests/ |
run-allregs.sh | 73 11: %st0 (st0), float 80 bits 145 33: %st0 (st0), float 80 bits [all...] |
run-readelf-mixed-corenote.sh | 576 st0: 0x00000000000000000000 st1: 0x00000000000000000000
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run-addrcfi.sh | 44 x87 reg11 (%st0): undefined 91 x87 reg11 (%st0): undefined 165 x87 reg33 (%st0): undefined 231 x87 reg33 (%st0): undefined [all...] |
/external/mesa3d/src/mesa/x86/ |
assyntax.h | 210 #define ST0 %st(0) 212 #define ST0 %st [all...] |