| /external/drm_gralloc/ |
| gralloc_drm_nouveau.c | 71 int flags, tile_mode, tile_flags; local
76 tile_mode = 0;
102 tile_mode = 0x40;
104 tile_mode = 0x30;
106 tile_mode = 0x20;
108 tile_mode = 0x10;
110 tile_mode = 0x00;
114 align = NVC0_TILE_HEIGHT(tile_mode);
119 tile_mode = 4;
121 tile_mode = 3
[all...] |
| /external/mesa3d/src/gallium/drivers/nouveau/nv50/ |
| nv50_transfer.h | 18 uint16_t tile_mode; member in struct:nv50_m2mf_rect
|
| nv50_miptree.c | 35 uint32_t tile_mode = 0x000; local
37 if (ny > 64) tile_mode = 0x040; /* height 128 tiles */
39 if (ny > 32) tile_mode = 0x030; /* height 64 tiles */
41 if (ny > 16) tile_mode = 0x020; /* height 32 tiles */
43 if (ny > 8) tile_mode = 0x010; /* height 16 tiles */
46 return tile_mode;
48 if (tile_mode > 0x020)
49 tile_mode = 0x020;
51 if (nz > 16 && tile_mode < 0x020)
52 return tile_mode | 0x500; /* depth 32 tiles *
[all...] |
| nv50_resource.h | 43 uint32_t tile_mode; member in struct:nv50_miptree_level
|
| /external/mesa3d/src/gallium/drivers/nouveau/nvc0/ |
| nvc0_miptree.c | 177 mt->level[0].tile_mode = 0x10;
214 lvl->tile_mode = nvc0_tex_choose_tile_dims(nbx, nby, d, mt->layout_3d);
216 tsx = NVC0_TILE_SIZE_X(lvl->tile_mode); /* x is tile row pitch in bytes */
217 tsy = NVC0_TILE_SIZE_Y(lvl->tile_mode);
218 tsz = NVC0_TILE_SIZE_Z(lvl->tile_mode);
231 NVC0_TILE_SIZE(mt->level[0].tile_mode));
300 bo_config.nvc0.tile_mode = mt->level[0].tile_mode;
333 unsigned tds = NVC0_TILE_SHIFT_Z(mt->level[l].tile_mode);
334 unsigned ths = NVC0_TILE_SHIFT_Y(mt->level[l].tile_mode);
[all...] |
| /hardware/qcom/display/msm8909/gralloc/ |
| gr_adreno_info.h | 130 int tile_mode, int raster_mode,
134 int width, int height, int format, int tile_mode, int raster_mode, int padding_threshold,
|
| /hardware/qcom/display/msm8909w_3100/libgralloc1/ |
| gr_adreno_info.h | 130 int tile_mode, int raster_mode,
134 int width, int height, int format, int tile_mode, int raster_mode, int padding_threshold,
|
| /hardware/qcom/display/msm8996/libgralloc1/ |
| gr_adreno_info.h | 130 int tile_mode, int raster_mode,
134 int width, int height, int format, int tile_mode, int raster_mode, int padding_threshold,
|
| /hardware/qcom/display/msm8998/libgralloc1/ |
| gr_adreno_info.h | 130 int tile_mode, int raster_mode,
134 int width, int height, int format, int tile_mode, int raster_mode, int padding_threshold,
|
| /external/libdrm/nouveau/ |
| abi16.c | 298 bo->config.nvc0.tile_mode = info->tile_mode;
303 bo->config.nv50.tile_mode = info->tile_mode << 4;
306 bo->config.nv04.surf_pitch = info->tile_mode;
343 info->tile_mode = config->nvc0.tile_mode;
348 info->tile_mode = config->nv50.tile_mode >> 4;
351 info->tile_mode = config->nv04.surf_pitch
[all...] |
| /external/libdrm/radeon/ |
| radeon_surface.c | 1731 unsigned mode, tile_mode, stencil_tile_mode; local
1791 unsigned mode, tile_mode, stencil_tile_mode; local
2335 unsigned mode, tile_mode, stencil_tile_mode; local
2395 unsigned mode, tile_mode, stencil_tile_mode; local
[all...] |
| /external/libdrm/include/drm/ |
| nouveau_drm.h | 121 uint32_t tile_mode; member in struct:drm_nouveau_gem_info
127 uint32_t tile_mode; member in struct:drm_nouveau_gem_set_tiling
254 uint32_t tile_mode; member in struct:drm_nouveau_gem_map
|
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| si_dma.c | 146 unsigned tile_mode = info->si_tile_mode_array[index]; local
169 array_mode = G_009910_ARRAY_MODE(tile_mode);
182 bank_h = G_009910_BANK_HEIGHT(tile_mode);
183 bank_w = G_009910_BANK_WIDTH(tile_mode);
184 mt_aspect = G_009910_MACRO_TILE_ASPECT(tile_mode);
187 nbanks = G_009910_NUM_BANKS(tile_mode);
191 pipe_config = G_009910_PIPE_CONFIG(tile_mode);
192 mt = G_009910_MICRO_TILE_MODE(tile_mode);
|
| /hardware/qcom/display/msm8084/libgralloc/ |
| gr.h | 138 int tile_mode,
150 int tile_mode,
|
| /hardware/qcom/display/msm8226/libgralloc/ |
| gr.h | 138 int tile_mode,
150 int tile_mode,
|
| /hardware/qcom/display/msm8909/libgralloc/ |
| gr.h | 172 int tile_mode,
182 int tile_mode,
|
| /hardware/qcom/display/msm8909w_3100/libgralloc/ |
| gr.h | 172 int tile_mode,
182 int tile_mode,
|
| /hardware/qcom/display/msm8994/libgralloc/ |
| gr.h | 166 int tile_mode,
178 int tile_mode,
|
| /hardware/qcom/display/msm8996/libgralloc/ |
| gr.h | 177 int tile_mode,
189 int tile_mode,
|
| /external/mesa3d/src/gallium/winsys/radeon/drm/ |
| radeon_drm_surface.c | 54 uint32_t tile_mode; local
61 tile_mode = info->si_tile_mode_array[surf->tiling_index[0]];
64 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
66 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
|
| /cts/hostsidetests/security/securityPatch/CVE-2017-0333/ |
| local_poc.h | 38 uint32_t tile_mode; member in struct:drm_nouveau_gem_info
50 uint32_t tile_mode; member in struct:drm_nouveau_gem_set_tiling
161 uint32_t tile_mode; member in struct:drm_nouveau_gem_map
|
| /bionic/libc/kernel/uapi/drm/ |
| nouveau_drm.h | 42 __u32 tile_mode; member in struct:drm_nouveau_gem_info
|
| /external/kernel-headers/original/uapi/drm/ |
| nouveau_drm.h | 55 __u32 tile_mode; member in struct:drm_nouveau_gem_info
|
| /hardware/qcom/media/msm8996/libc2dcolorconvert/ |
| C2DColorConverter.h | 68 typedef void (*LINK_AdrenoComputeAlignedWidthAndHeight) (int width, int height, int bpp, int tile_mode, int raster_mode,
|
| /hardware/qcom/media/msm8998/libc2dcolorconvert/ |
| C2DColorConverter.h | 68 typedef void (*LINK_AdrenoComputeAlignedWidthAndHeight) (int width, int height, int bpp, int tile_mode, int raster_mode,
|
