| /external/mesa3d/src/amd/addrlib/inc/chip/r800/ |
| si_gb_reg.h | 100 unsigned int tile_split : 3; member in struct:_GB_TILE_MODE_T
128 unsigned int tile_split : 3; member in struct:_GB_TILE_MODE_T
|
| /external/libdrm/radeon/ |
| radeon_surface.c | 658 unsigned bpe, unsigned tile_split,
672 if (tileb > tile_split && tile_split) {
673 slice_pt = tileb / tile_split;
737 switch (surf->tile_split) {
782 tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples);
824 surf->tile_split, 0, 0);
908 /* compute best tile_split, bankw, bankh, mtilea
921 surf->tile_split = 1024;
925 tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples)
1874 unsigned tile_split, sample_split; local
[all...] |
| radeon_surface.h | 133 uint32_t tile_split; member in struct:radeon_surface
|
| /external/mesa3d/src/gallium/winsys/radeon/drm/ |
| radeon_drm_surface.c | 39 tileb = MIN2(surf->tile_split, tileb);
157 surf_drm->tile_split = surf_ws->tile_split;
198 surf_ws->tile_split = surf_drm->tile_split;
|
| radeon_drm_bo.c | 829 static unsigned eg_tile_split(unsigned tile_split)
831 switch (tile_split) {
832 case 0: tile_split = 64; break;
833 case 1: tile_split = 128; break;
834 case 2: tile_split = 256; break;
835 case 3: tile_split = 512; break;
837 case 4: tile_split = 1024; break;
838 case 5: tile_split = 2048; break;
839 case 6: tile_split = 4096; break;
841 return tile_split;
[all...] |
| /external/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| amdgpu_bo.c | 566 static unsigned eg_tile_split(unsigned tile_split)
568 switch (tile_split) {
569 case 0: tile_split = 64; break;
570 case 1: tile_split = 128; break;
571 case 2: tile_split = 256; break;
572 case 3: tile_split = 512; break;
574 case 4: tile_split = 1024; break;
575 case 5: tile_split = 2048; break;
576 case 6: tile_split = 4096; break;
578 return tile_split;
[all...] |
| amdgpu_surface.c | 291 tileb = MIN2(surf->tile_split, tileb);
439 surf->bankw && surf->bankh && surf->mtilea && surf->tile_split) {
448 AddrTileInfoIn.tileSplitBytes = surf->tile_split;
517 surf->tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
|
| /external/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| radv_amdgpu_surface.c | 282 tileb = MIN2(surf->tile_split, tileb);
407 surf->bankw && surf->bankh && surf->mtilea && surf->tile_split) {
414 AddrTileInfoIn.tileSplitBytes = surf->tile_split;
476 surf->tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
|
| radv_amdgpu_bo.c | 270 if (md->tile_split)
271 tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, radv_eg_tile_split_rev(md->tile_split));
|
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| si_dma.c | 150 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, mt; local
185 /* Non-depth modes don't have TILE_SPLIT set. */
186 tile_split = util_logbase2(rtiled->surface.tile_split >> 6);
211 radeon_emit(cs, (tiled_y << 0) | (tile_split << 21) | (nbanks << 25) | (mt << 27));
|
| cik_sdma.c | 131 /* Non-depth modes don't have TILE_SPLIT set. */
132 ((util_logbase2(tex->surface.tile_split >> 6)) << 11) |
382 tiled->surface.tile_split <= 4096 &&
426 rsrc->surface.tile_split <= 4096 &&
427 rdst->surface.tile_split <= 4096 &&
|
| /external/mesa3d/src/gallium/drivers/r600/ |
| evergreen_state.c | 63 static unsigned eg_tile_split(unsigned tile_split)
65 switch (tile_split) {
66 case 64: tile_split = 0; break;
67 case 128: tile_split = 1; break;
68 case 256: tile_split = 2; break;
69 case 512: tile_split = 3; break;
71 case 1024: tile_split = 4; break;
72 case 2048: tile_split = 5; break;
73 case 4096: tile_split = 6; break;
75 return tile_split;
670 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh; local
997 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks; local
1173 unsigned macro_aspect, tile_split, bankh, bankw, nbanks; local
3357 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0; local
[all...] |
| /external/mesa3d/src/amd/vulkan/ |
| radv_radeon_winsys.h | 198 uint32_t tile_split; member in struct:radeon_surf
240 unsigned tile_split; member in struct:radeon_bo_metadata
|
| radv_image.c | 445 metadata->tile_split = surface->tile_split;
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| radeon_video.c | 172 surfaces[i]->tile_split = surfaces[best_tiling]->tile_split;
|
| radeon_winsys.h | 240 unsigned tile_split; member in struct:radeon_bo_metadata
326 unsigned tile_split:13; /* max 4K */ member in struct:radeon_surf
|
| r600_texture.c | 294 metadata->tile_split = surface->tile_split;
602 fmask.tile_split = rtex->surface.tile_split;
915 rtex->surface.tile_split, rtex->surface.pipe_config,
[all...] |
| /external/mesa3d/src/amd/addrlib/r800/ |
| ciaddrlib.cpp | 565 // Here we used tile_bytes to replace of tile_split
567 // "tile_split_c = MIN(ROW_SIZE, tile_split)
569 // when using tile_bytes replacing of tile_split, the result of
572 // (num_samples * tile_bytes_1x is larger), a correct tile_split is
[all...] |
| siaddrlib.cpp | [all...] |
