| /hardware/intel/img/hwcomposer/merrifield/include/ |
| IVideoPayloadManager.h | 43 bool tiled; member in struct:android::intel::IVideoPayloadManager::Buffer
|
| /external/tensorflow/tensorflow/python/kernel_tests/ |
| shape_ops_test.py | 417 tiled = array_ops.tile(a, [])
418 result = tiled.eval()
420 self.assertEqual([], tiled.get_shape())
429 tiled = array_ops.tile(a, constant_op.constant([1, 4], dtype=dtype))
430 result = tiled.eval()
432 self.assertEqual([4, 4], tiled.get_shape())
439 tiled = array_ops.tile(a, [1, 1])
440 result = tiled.eval()
442 self.assertEqual([4, 1], tiled.get_shape())
449 tiled = array_ops.tile(a, [5, 0]
[all...] |
| /hardware/intel/img/hwcomposer/merrifield/ips/common/ |
| VideoPayloadManager.cpp | 62 metadata->normalBuffer.tiled = (p->width > 1280);
74 metadata->scalingBuffer.tiled = false;
100 metadata->rotationBuffer.tiled = metadata->normalBuffer.tiled;
|
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| cik_sdma.c | 255 /* Tiled <-> linear sub-window copy. */
257 struct r600_texture *tiled = src_mode >= RADEON_SURF_MODE_1D ? rsrc : rdst; local
258 struct r600_texture *linear = tiled == rsrc ? rdst : rsrc;
259 unsigned tiled_level = tiled == rsrc ? src_level : dst_level;
261 unsigned tiled_x = tiled == rsrc ? srcx : dstx;
263 unsigned tiled_y = tiled == rsrc ? srcy : dsty;
265 unsigned tiled_z = tiled == rsrc ? srcz : dstz;
267 unsigned tiled_width = tiled == rsrc ? src_width : dst_width;
269 unsigned tiled_pitch = tiled == rsrc ? src_pitch : dst_pitch;
271 unsigned tiled_slice_pitch = tiled == rsrc ? src_slice_pitch : dst_slice_pitch
[all...] |
| /external/drm_gralloc/ |
| gralloc_drm_nouveau.c | 72 int tiled, scanout; local
81 tiled = !(usage & (GRALLOC_USAGE_SW_READ_OFTEN |
84 tiled = 0;
86 tiled = 1;
94 tiled = 1;
99 if (tiled) {
254 /* TODO if tiled, allocate a linear copy of bo in GART and map it */
266 /* TODO if tiled, unmap the linear bo and copy back */
|
| /bionic/libc/kernel/uapi/drm/ |
| omap_drm.h | 44 } tiled; member in union:omap_gem_size
|
| /external/kernel-headers/original/uapi/drm/ |
| omap_drm.h | 43 #define OMAP_BO_TILED_MASK 0x00000f00 /* tiled mapping mask, see tiled modes */
50 /* tiled modes */
57 __u32 bytes; /* (for non-tiled formats) */
61 } tiled; /* (for tiled formats) */ member in union:omap_gem_size
97 /* note: in case of tiled buffers, the user virtual size can be
|
| /external/mesa3d/src/gallium/drivers/vc4/ |
| vc4_resource.h | 60 bool tiled; member in struct:vc4_resource
|
| vc4_resource.c | 276 if (rsc->tiled) {
280 /* No direct mappings of tiled, since we need to manually
427 if (!rsc->tiled) {
528 if (!rsc->tiled) {
556 rsc->tiled = false;
558 rsc->tiled = true;
604 rsc->tiled = false;
[all...] |
| /external/libdrm/omap/ |
| omap_drm.h | 54 #define OMAP_BO_TILED_MASK 0x00000f00 /* tiled mapping mask, see tiled modes */
61 /* tiled modes */
68 uint32_t bytes; /* (for non-tiled formats) */
72 } tiled; /* (for tiled formats) */ member in union:omap_gem_size
108 /* note: in case of tiled buffers, the user virtual size can be
|
| omap_drm.c | 219 bo->size = round_up(size.tiled.width, PAGE_SIZE) * size.tiled.height;
232 /* allocate a new (un-tiled) buffer object */
251 .tiled = {
|
| /external/mesa3d/src/amd/vulkan/ |
| radv_formats.c | 546 VkFormatFeatureFlags linear = 0, tiled = 0, buffer = 0; local
551 out_properties->optimalTilingFeatures = tiled;
557 tiled |= VK_FORMAT_FEATURE_STORAGE_IMAGE_BIT;
569 tiled |= VK_FORMAT_FEATURE_DEPTH_STENCIL_ATTACHMENT_BIT;
570 tiled |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT;
571 tiled |= VK_FORMAT_FEATURE_BLIT_SRC_BIT |
578 tiled |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT |
582 tiled |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_LINEAR_BIT;
587 tiled |= VK_FORMAT_FEATURE_COLOR_ATTACHMENT_BIT | VK_FORMAT_FEATURE_BLIT_DST_BIT;
590 tiled |= VK_FORMAT_FEATURE_COLOR_ATTACHMENT_BLEND_BIT
[all...] |
| /external/mesa3d/src/intel/vulkan/ |
| anv_formats.c | 283 /* Tiled formats *must* be power-of-two because we need up upload
387 VkFormatFeatureFlags linear = 0, tiled = 0, buffer = 0; local
391 tiled |= VK_FORMAT_FEATURE_DEPTH_STENCIL_ATTACHMENT_BIT;
393 tiled |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT;
395 tiled |= VK_FORMAT_FEATURE_BLIT_SRC_BIT |
408 tiled = get_image_format_properties(&physical_device->info,
423 tiled &= ~VK_FORMAT_FEATURE_COLOR_ATTACHMENT_BIT &
427 /* ASTC textures must be in Y-tiled memory */
433 out_properties->optimalTilingFeatures = tiled;
|
| /external/mesa3d/src/gallium/drivers/etnaviv/ |
| etnaviv_resource.c | 254 /* Keep single byte blocksized resources as tiled, since we
257 * must be multi-tiled for GPUs with multiple pixel pipes.
355 /* Render targets are linear in Xorg but must be tiled
358 struct etna_resource *tiled; local
364 tiled = etna_resource(ptiled);
365 tiled->scanout = renderonly_scanout_for_prime(prsc, screen->ro);
366 if (!tiled->scanout)
|
| /external/tensorflow/tensorflow/contrib/seq2seq/python/ops/ |
| beam_search_decoder.py | 86 tiled = array_ops.tile(array_ops.expand_dims(t, 1), tiling)
87 tiled = array_ops.reshape(tiled,
90 tiled.set_shape(
93 return tiled
139 - The encoder output has been tiled to `beam_width` via
144 `cell_state` value containing properly tiled final state from the
|
| /hardware/intel/img/psb_video/src/ |
| vsp_VPP.c | 408 unsigned int tiled = 0, width = 0, height = 0, stride = 0; local
548 tiled = GET_SURFACE_INFO_tiling(input_surface->psb_surface);
584 cell_proc_picture_param->input_picture[0].tiled = tiled;
631 if (tiled && rotation_angle != VA_ROTATION_NONE) {
641 if (tiled && rotation_angle != VA_ROTATION_NONE) {
693 cell_proc_picture_param->output_picture[i].tiled = tiled;
[all...] |
| vsp_fw.h | 126 /* flag indicating if frame is stored in tiled format */
127 unsigned int tiled; member in struct:VssProcPicture
|
| /external/mesa3d/src/gallium/drivers/ilo/ |
| ilo_transfer.c | 87 bool tiled; local
90 tiled = false;
116 tiled = (tex->image.tiling != GEN6_TILING_NONE);
119 if (tiled)
412 * tiled region are numbered in row-major order, starting from zero. The
422 * and the tiled offset is
442 * tiled region are numbered in row-major order, starting from zero. The
452 * and the tiled offset is
472 * tiled region are numbered in row-major order, starting from zero. The
490 * and the tiled offset i
[all...] |
| /device/linaro/hikey/gralloc960/ |
| Android.mk | 35 # GPU support for AFBC 1.2 tiled headers
|
| /external/skia/gm/ |
| multipicturedraw.cpp | 87 // Create a picture that consists of a single large layer that is tiled
387 static void tiled(SkCanvas* finalCanvas, SkMultiPictureDraw* mpd, function
426 constexpr PFLayoutMtd gLayoutMthds[] = { simple, tiled };
432 * tiled vs. all-at-once rendering (e.g., into many or just 1 canvas)
515 const char* gLayoutNames[] = { "simple", "tiled" };
|
| /external/skqp/gm/ |
| multipicturedraw.cpp | 87 // Create a picture that consists of a single large layer that is tiled
387 static void tiled(SkCanvas* finalCanvas, SkMultiPictureDraw* mpd, function
426 constexpr PFLayoutMtd gLayoutMthds[] = { simple, tiled };
432 * tiled vs. all-at-once rendering (e.g., into many or just 1 canvas)
515 const char* gLayoutNames[] = { "simple", "tiled" };
|
| /hardware/intel/img/hwcomposer/merrifield/common/devices/ |
| VirtualDevice.cpp | 209 VAMappedHandle(VADisplay dpy, buffer_handle_t khandle, uint32_t stride, uint32_t height, bool tiled)
222 attribTpi.tiling = tiled;
265 VAMappedHandleObject(VADisplay dpy, buffer_handle_t khandle, uint32_t stride, uint32_t height, bool tiled)
266 : VAMappedHandle(dpy, khandle, stride, height, tiled) { }
[all...] |
| /hardware/qcom/display/msm8996/libgralloc/ |
| alloc_controller.cpp | 720 int& alignedw, int &alignedh, int& tiled, unsigned int& size)
722 tiled = isUBwcEnabled(format, usage) || isMacroTileEnabled(format, usage);
[all...] |
