| /external/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| radv_amdgpu_bo.c | 258 uint32_t tiling_flags = 0; local
261 tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4); /* 2D_TILED_THIN1 */
263 tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2); /* 1D_TILED_THIN1 */
265 tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1); /* LINEAR_ALIGNED */
267 tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, md->pipe_config);
268 tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(md->bankw));
269 tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(md->bankh));
271 tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, radv_eg_tile_split_rev(md->tile_split));
272 tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(md->mtilea));
273 tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(md->num_banks)-1)
[all...] |
| /external/libdrm/radeon/ |
| radeon_bo.h | 68 int radeon_bo_set_tiling(struct radeon_bo *bo, uint32_t tiling_flags, uint32_t pitch);
69 int radeon_bo_get_tiling(struct radeon_bo *bo, uint32_t *tiling_flags, uint32_t *pitch);
|
| radeon_bo_int.h | 37 int (*bo_set_tiling)(struct radeon_bo_int *bo, uint32_t tiling_flags,
39 int (*bo_get_tiling)(struct radeon_bo_int *bo, uint32_t *tiling_flags,
|
| radeon_bo.c | 101 uint32_t tiling_flags, uint32_t pitch)
104 return boi->bom->funcs->bo_set_tiling(boi, tiling_flags, pitch);
109 uint32_t *tiling_flags, uint32_t *pitch)
112 return boi->bom->funcs->bo_get_tiling(boi, tiling_flags, pitch);
|
| radeon_bo_gem.c | 235 static int bo_set_tiling(struct radeon_bo_int *boi, uint32_t tiling_flags,
242 args.tiling_flags = tiling_flags;
252 static int bo_get_tiling(struct radeon_bo_int *boi, uint32_t *tiling_flags,
268 *tiling_flags = args.tiling_flags;
|
| /external/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| amdgpu_bo.c | 600 uint32_t tiling_flags; local
609 tiling_flags = info.metadata.tiling_info;
614 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 4) /* 2D_TILED_THIN1 */
616 else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 2) /* 1D_TILED_THIN1 */
619 md->pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
620 md->bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
621 md->bankh = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
622 md->tile_split = eg_tile_split(AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT));
623 md->mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
624 md->num_banks = 2 << AMDGPU_TILING_GET(tiling_flags, NUM_BANKS)
636 uint32_t tiling_flags = 0; local
[all...] |
| /external/mesa3d/src/intel/isl/tests/ |
| isl_surf_get_image_offset_test.c | 145 .tiling_flags = ISL_TILING_Y0_BIT);
193 .tiling_flags = ISL_TILING_Y0_BIT);
254 .tiling_flags = ISL_TILING_Y0_BIT);
|
| /external/mesa3d/src/gallium/winsys/radeon/drm/ |
| radeon_drm_bo.c | 877 if (args.tiling_flags & RADEON_TILING_MICRO)
879 else if (args.tiling_flags & RADEON_TILING_MICRO_SQUARE)
882 if (args.tiling_flags & RADEON_TILING_MACRO)
885 md->bankw = (args.tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
886 md->bankh = (args.tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
887 md->tile_split = (args.tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
888 md->mtilea = (args.tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
890 md->scanout = bo->rws->gen >= DRV_SI && !(args.tiling_flags & RADEON_TILING_R600_NO_SCANOUT);
906 args.tiling_flags |= RADEON_TILING_MICRO;
908 args.tiling_flags |= RADEON_TILING_MICRO_SQUARE
[all...] |
| /external/mesa3d/src/intel/isl/ |
| isl.c | 256 isl_tiling_flags_t tiling_flags = info->tiling_flags; local
261 assert(tiling_flags == ISL_TILING_HIZ_BIT);
269 assert(tiling_flags == ISL_TILING_CCS_BIT);
275 isl_gen6_filter_tiling(dev, info, &tiling_flags);
278 isl_gen6_filter_tiling(dev, info, &tiling_flags);
283 if (tiling_flags & (1u << (__tiling))) { \
[all...] |
| isl.h | 819 isl_tiling_flags_t tiling_flags; member in struct:isl_surf_init_info
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| radeon_common_context.c | 512 uint32_t tiling_flags = 0, pitch = 0; local
528 ret = radeon_bo_get_tiling(bo, &tiling_flags, &pitch);
537 if (tiling_flags & RADEON_TILING_MACRO)
539 if (tiling_flags & RADEON_TILING_MICRO)
|
| /external/mesa3d/src/intel/vulkan/ |
| anv_image.c | 141 isl_tiling_flags_t tiling_flags = local
146 tiling_flags &= anv_info->isl_tiling_flags;
148 assert(tiling_flags);
171 .tiling_flags = tiling_flags);
|
| anv_blorp.c | 165 .tiling_flags = ISL_TILING_LINEAR_BIT);
559 .tiling_flags = ISL_TILING_LINEAR_BIT);
[all...] |
| /bionic/libc/kernel/uapi/drm/ |
| radeon_drm.h | 647 __u32 tiling_flags; member in struct:drm_radeon_gem_set_tiling
652 __u32 tiling_flags; member in struct:drm_radeon_gem_get_tiling
|
| /external/kernel-headers/original/uapi/drm/ |
| radeon_drm.h | 858 __u32 tiling_flags; member in struct:drm_radeon_gem_set_tiling
864 __u32 tiling_flags; member in struct:drm_radeon_gem_get_tiling
[all...] |
| /external/libdrm/include/drm/ |
| radeon_drm.h | 859 uint32_t tiling_flags; member in struct:drm_radeon_gem_set_tiling
865 uint32_t tiling_flags; member in struct:drm_radeon_gem_get_tiling
[all...] |
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.15-4.8/sysroot/usr/include/drm/ |
| radeon_drm.h | 815 uint32_t tiling_flags; member in struct:drm_radeon_gem_set_tiling
821 uint32_t tiling_flags; member in struct:drm_radeon_gem_get_tiling
[all...] |
| /external/mesa3d/src/intel/blorp/ |
| blorp_blit.c | [all...] |
