/external/llvm/test/MC/X86/ |
x86-64-avx512cd.s | 23 // CHECK: vplzcntq (%rcx){1to8}, %zmm21 25 vplzcntq (%rcx){1to8}, %zmm21 43 // CHECK: vplzcntq 1016(%rdx){1to8}, %zmm21 45 vplzcntq 1016(%rdx){1to8}, %zmm21 47 // CHECK: vplzcntq 1024(%rdx){1to8}, %zmm21 49 vplzcntq 1024(%rdx){1to8}, %zmm21 51 // CHECK: vplzcntq -1024(%rdx){1to8}, %zmm21 53 vplzcntq -1024(%rdx){1to8}, %zmm21 55 // CHECK: vplzcntq -1032(%rdx){1to8}, %zmm21 57 vplzcntq -1032(%rdx){1to8}, %zmm21 [all...] |
avx512ifma-encoding.s | 35 vpmadd52luq (%rcx){1to8}, %zmm29, %zmm30 36 //CHECK: vpmadd52luq (%rcx){1to8}, %zmm29, %zmm30 55 vpmadd52luq 0x3f8(%rdx){1to8}, %zmm29, %zmm30 56 //CHECK: vpmadd52luq 1016(%rdx){1to8}, %zmm29, %zmm30 59 vpmadd52luq 0x400(%rdx){1to8}, %zmm29, %zmm30 60 //CHECK: vpmadd52luq 1024(%rdx){1to8}, %zmm29, %zmm30 63 vpmadd52luq -0x400(%rdx){1to8}, %zmm29, %zmm30 64 //CHECK: vpmadd52luq -1024(%rdx){1to8}, %zmm29, %zmm30 67 vpmadd52luq -0x408(%rdx){1to8}, %zmm29, %zmm30 68 //CHECK: vpmadd52luq -1032(%rdx){1to8}, %zmm29, %zmm3 [all...] |
x86-64-avx512dq.s | 23 // CHECK: vpmullq (%rcx){1to8}, %zmm24, %zmm18 25 vpmullq (%rcx){1to8}, %zmm24, %zmm18 43 // CHECK: vpmullq 1016(%rdx){1to8}, %zmm24, %zmm18 45 vpmullq 1016(%rdx){1to8}, %zmm24, %zmm18 47 // CHECK: vpmullq 1024(%rdx){1to8}, %zmm24, %zmm18 49 vpmullq 1024(%rdx){1to8}, %zmm24, %zmm18 51 // CHECK: vpmullq -1024(%rdx){1to8}, %zmm24, %zmm18 53 vpmullq -1024(%rdx){1to8}, %zmm24, %zmm18 55 // CHECK: vpmullq -1032(%rdx){1to8}, %zmm24, %zmm18 57 vpmullq -1032(%rdx){1to8}, %zmm24, %zmm1 [all...] |
x86-64-avx512cd_vl.s | 303 // CHECK: vplzcntd (%rcx){1to8}, %ymm25 305 vplzcntd (%rcx){1to8}, %ymm25 323 // CHECK: vplzcntd 508(%rdx){1to8}, %ymm25 325 vplzcntd 508(%rdx){1to8}, %ymm25 327 // CHECK: vplzcntd 512(%rdx){1to8}, %ymm25 329 vplzcntd 512(%rdx){1to8}, %ymm25 331 // CHECK: vplzcntd -512(%rdx){1to8}, %ymm25 333 vplzcntd -512(%rdx){1to8}, %ymm25 335 // CHECK: vplzcntd -516(%rdx){1to8}, %ymm25 337 vplzcntd -516(%rdx){1to8}, %ymm2 [all...] |
intel-syntax-avx512.s | 63 // CHECK: vcmppd k2, zmm12, qword ptr [rcx]{1to8}, 123 65 vcmppd k2,zmm12,QWORD PTR [rcx]{1to8},0x7b 83 // CHECK: vcmppd k2, zmm12, qword ptr [rdx + 1016]{1to8}, 123 85 vcmppd k2,zmm12,QWORD PTR [rdx+0x3f8]{1to8},0x7b 87 // CHECK: vcmppd k2, zmm12, qword ptr [rdx + 1024]{1to8}, 123 89 vcmppd k2,zmm12,QWORD PTR [rdx+0x400]{1to8},0x7b 91 // CHECK: vcmppd k2, zmm12, qword ptr [rdx - 1024]{1to8}, 123 93 vcmppd k2,zmm12,QWORD PTR [rdx-0x400]{1to8},0x7b 95 // CHECK: vcmppd k2, zmm12, qword ptr [rdx - 1032]{1to8}, 123 97 vcmppd k2,zmm12,QWORD PTR [rdx-0x408]{1to8},0x7 [all...] |
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/i386/ |
avx512ifma.s | 11 vpmadd52luq (%eax){1to8}, %zmm5, %zmm6 # AVX512IFMA 16 vpmadd52luq 1016(%edx){1to8}, %zmm5, %zmm6 # AVX512IFMA Disp8 17 vpmadd52luq 1024(%edx){1to8}, %zmm5, %zmm6 # AVX512IFMA 18 vpmadd52luq -1024(%edx){1to8}, %zmm5, %zmm6 # AVX512IFMA Disp8 19 vpmadd52luq -1032(%edx){1to8}, %zmm5, %zmm6 # AVX512IFMA 25 vpmadd52huq (%eax){1to8}, %zmm5, %zmm6 # AVX512IFMA 30 vpmadd52huq 1016(%edx){1to8}, %zmm5, %zmm6 # AVX512IFMA Disp8 31 vpmadd52huq 1024(%edx){1to8}, %zmm5, %zmm6 # AVX512IFMA 32 vpmadd52huq -1024(%edx){1to8}, %zmm5, %zmm6 # AVX512IFMA Disp8 33 vpmadd52huq -1032(%edx){1to8}, %zmm5, %zmm6 # AVX512IFM [all...] |
x86-64-avx512ifma.s | 11 vpmadd52luq (%rcx){1to8}, %zmm29, %zmm30 # AVX512IFMA 16 vpmadd52luq 1016(%rdx){1to8}, %zmm29, %zmm30 # AVX512IFMA Disp8 17 vpmadd52luq 1024(%rdx){1to8}, %zmm29, %zmm30 # AVX512IFMA 18 vpmadd52luq -1024(%rdx){1to8}, %zmm29, %zmm30 # AVX512IFMA Disp8 19 vpmadd52luq -1032(%rdx){1to8}, %zmm29, %zmm30 # AVX512IFMA 25 vpmadd52huq (%rcx){1to8}, %zmm29, %zmm30 # AVX512IFMA 30 vpmadd52huq 1016(%rdx){1to8}, %zmm29, %zmm30 # AVX512IFMA Disp8 31 vpmadd52huq 1024(%rdx){1to8}, %zmm29, %zmm30 # AVX512IFMA 32 vpmadd52huq -1024(%rdx){1to8}, %zmm29, %zmm30 # AVX512IFMA Disp8 33 vpmadd52huq -1032(%rdx){1to8}, %zmm29, %zmm30 # AVX512IFM [all...] |
x86-64-avx512ifma-intel.d | 17 [ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 31[ ]*vpmadd52luq zmm30,zmm29,QWORD PTR \[rcx\]\{1to8\} 22 [ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 72 7f[ ]*vpmadd52luq zmm30,zmm29,QWORD PTR \[rdx\+0x3f8\]\{1to8\} 23 [ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 b2 00 04 00 00[ ]*vpmadd52luq zmm30,zmm29,QWORD PTR \[rdx\+0x400\]\{1to8\} 24 [ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 72 80[ ]*vpmadd52luq zmm30,zmm29,QWORD PTR \[rdx-0x400\]\{1to8\} 25 [ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 b2 f8 fb ff ff[ ]*vpmadd52luq zmm30,zmm29,QWORD PTR \[rdx-0x408\]\{1to8\} 31 [ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 31[ ]*vpmadd52huq zmm30,zmm29,QWORD PTR \[rcx\]\{1to8\} 36 [ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 72 7f[ ]*vpmadd52huq zmm30,zmm29,QWORD PTR \[rdx\+0x3f8\]\{1to8\} 37 [ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 b2 00 04 00 00[ ]*vpmadd52huq zmm30,zmm29,QWORD PTR \[rdx\+0x400\]\{1to8\} 38 [ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 72 80[ ]*vpmadd52huq zmm30,zmm29,QWORD PTR \[rdx-0x400\]\{1to8\} 39 [ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 b2 f8 fb ff ff[ ]*vpmadd52huq zmm30,zmm29,QWORD PTR \[rdx-0x408\]\{1to8\} [all...] |
x86-64-avx512ifma.d | 17 [ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 31[ ]*vpmadd52luq \(%rcx\)\{1to8\},%zmm29,%zmm30 22 [ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 72 7f[ ]*vpmadd52luq 0x3f8\(%rdx\)\{1to8\},%zmm29,%zmm30 23 [ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 b2 00 04 00 00[ ]*vpmadd52luq 0x400\(%rdx\)\{1to8\},%zmm29,%zmm30 24 [ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 72 80[ ]*vpmadd52luq -0x400\(%rdx\)\{1to8\},%zmm29,%zmm30 25 [ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 b2 f8 fb ff ff[ ]*vpmadd52luq -0x408\(%rdx\)\{1to8\},%zmm29,%zmm30 31 [ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 31[ ]*vpmadd52huq \(%rcx\)\{1to8\},%zmm29,%zmm30 36 [ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 72 7f[ ]*vpmadd52huq 0x3f8\(%rdx\)\{1to8\},%zmm29,%zmm30 37 [ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 b2 00 04 00 00[ ]*vpmadd52huq 0x400\(%rdx\)\{1to8\},%zmm29,%zmm30 38 [ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 72 80[ ]*vpmadd52huq -0x400\(%rdx\)\{1to8\},%zmm29,%zmm30 39 [ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 b2 f8 fb ff ff[ ]*vpmadd52huq -0x408\(%rdx\)\{1to8\},%zmm29,%zmm3 [all...] |
avx512cd.s | 27 vpconflictq (%eax){1to8}, %zmm6 # AVX512CD 32 vpconflictq 1016(%edx){1to8}, %zmm6 # AVX512CD Disp8 33 vpconflictq 1024(%edx){1to8}, %zmm6 # AVX512CD 34 vpconflictq -1024(%edx){1to8}, %zmm6 # AVX512CD Disp8 35 vpconflictq -1032(%edx){1to8}, %zmm6 # AVX512CD 57 vplzcntq (%eax){1to8}, %zmm6 # AVX512CD 62 vplzcntq 1016(%edx){1to8}, %zmm6 # AVX512CD Disp8 63 vplzcntq 1024(%edx){1to8}, %zmm6 # AVX512CD 64 vplzcntq -1024(%edx){1to8}, %zmm6 # AVX512CD Disp8 65 vplzcntq -1032(%edx){1to8}, %zmm6 # AVX512C [all...] |
x86-64-avx512cd.s | 27 vpconflictq (%rcx){1to8}, %zmm30 # AVX512CD 32 vpconflictq 1016(%rdx){1to8}, %zmm30 # AVX512CD Disp8 33 vpconflictq 1024(%rdx){1to8}, %zmm30 # AVX512CD 34 vpconflictq -1024(%rdx){1to8}, %zmm30 # AVX512CD Disp8 35 vpconflictq -1032(%rdx){1to8}, %zmm30 # AVX512CD 57 vplzcntq (%rcx){1to8}, %zmm30 # AVX512CD 62 vplzcntq 1016(%rdx){1to8}, %zmm30 # AVX512CD Disp8 63 vplzcntq 1024(%rdx){1to8}, %zmm30 # AVX512CD 64 vplzcntq -1024(%rdx){1to8}, %zmm30 # AVX512CD Disp8 65 vplzcntq -1032(%rdx){1to8}, %zmm30 # AVX512C [all...] |
avx512dq.s | 56 vcvtpd2qq (%eax){1to8}, %zmm6 # AVX512DQ 61 vcvtpd2qq 1016(%edx){1to8}, %zmm6 # AVX512DQ Disp8 62 vcvtpd2qq 1024(%edx){1to8}, %zmm6 # AVX512DQ 63 vcvtpd2qq -1024(%edx){1to8}, %zmm6 # AVX512DQ Disp8 64 vcvtpd2qq -1032(%edx){1to8}, %zmm6 # AVX512DQ 74 vcvtpd2uqq (%eax){1to8}, %zmm6 # AVX512DQ 79 vcvtpd2uqq 1016(%edx){1to8}, %zmm6 # AVX512DQ Disp8 80 vcvtpd2uqq 1024(%edx){1to8}, %zmm6 # AVX512DQ 81 vcvtpd2uqq -1024(%edx){1to8}, %zmm6 # AVX512DQ Disp8 82 vcvtpd2uqq -1032(%edx){1to8}, %zmm6 # AVX512D [all...] |
avx512ifma-intel.d | 17 [ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 30[ ]*vpmadd52luq zmm6,zmm5,QWORD PTR \[eax\]\{1to8\} 22 [ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 72 7f[ ]*vpmadd52luq zmm6,zmm5,QWORD PTR \[edx\+0x3f8\]\{1to8\} 23 [ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 b2 00 04 00 00[ ]*vpmadd52luq zmm6,zmm5,QWORD PTR \[edx\+0x400\]\{1to8\} 24 [ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 72 80[ ]*vpmadd52luq zmm6,zmm5,QWORD PTR \[edx-0x400\]\{1to8\} 25 [ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 b2 f8 fb ff ff[ ]*vpmadd52luq zmm6,zmm5,QWORD PTR \[edx-0x408\]\{1to8\} 31 [ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 30[ ]*vpmadd52huq zmm6,zmm5,QWORD PTR \[eax\]\{1to8\} 36 [ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 72 7f[ ]*vpmadd52huq zmm6,zmm5,QWORD PTR \[edx\+0x3f8\]\{1to8\} 37 [ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 b2 00 04 00 00[ ]*vpmadd52huq zmm6,zmm5,QWORD PTR \[edx\+0x400\]\{1to8\} 38 [ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 72 80[ ]*vpmadd52huq zmm6,zmm5,QWORD PTR \[edx-0x400\]\{1to8\} 39 [ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 b2 f8 fb ff ff[ ]*vpmadd52huq zmm6,zmm5,QWORD PTR \[edx-0x408\]\{1to8\} [all...] |
avx512ifma.d | 17 [ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 30[ ]*vpmadd52luq \(%eax\)\{1to8\},%zmm5,%zmm6 22 [ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 72 7f[ ]*vpmadd52luq 0x3f8\(%edx\)\{1to8\},%zmm5,%zmm6 23 [ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 b2 00 04 00 00[ ]*vpmadd52luq 0x400\(%edx\)\{1to8\},%zmm5,%zmm6 24 [ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 72 80[ ]*vpmadd52luq -0x400\(%edx\)\{1to8\},%zmm5,%zmm6 25 [ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 b2 f8 fb ff ff[ ]*vpmadd52luq -0x408\(%edx\)\{1to8\},%zmm5,%zmm6 31 [ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 30[ ]*vpmadd52huq \(%eax\)\{1to8\},%zmm5,%zmm6 36 [ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 72 7f[ ]*vpmadd52huq 0x3f8\(%edx\)\{1to8\},%zmm5,%zmm6 37 [ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 b2 00 04 00 00[ ]*vpmadd52huq 0x400\(%edx\)\{1to8\},%zmm5,%zmm6 38 [ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 72 80[ ]*vpmadd52huq -0x400\(%edx\)\{1to8\},%zmm5,%zmm6 39 [ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 b2 f8 fb ff ff[ ]*vpmadd52huq -0x408\(%edx\)\{1to8\},%zmm5,%zmm [all...] |
x86-64-avx512dq.s | 56 vcvtpd2qq (%rcx){1to8}, %zmm30 # AVX512DQ 61 vcvtpd2qq 1016(%rdx){1to8}, %zmm30 # AVX512DQ Disp8 62 vcvtpd2qq 1024(%rdx){1to8}, %zmm30 # AVX512DQ 63 vcvtpd2qq -1024(%rdx){1to8}, %zmm30 # AVX512DQ Disp8 64 vcvtpd2qq -1032(%rdx){1to8}, %zmm30 # AVX512DQ 74 vcvtpd2uqq (%rcx){1to8}, %zmm30 # AVX512DQ 79 vcvtpd2uqq 1016(%rdx){1to8}, %zmm30 # AVX512DQ Disp8 80 vcvtpd2uqq 1024(%rdx){1to8}, %zmm30 # AVX512DQ 81 vcvtpd2uqq -1024(%rdx){1to8}, %zmm30 # AVX512DQ Disp8 82 vcvtpd2uqq -1032(%rdx){1to8}, %zmm30 # AVX512D [all...] |
inval-avx512f.s | 12 vcvtps2pd (%eax), %zmm1{1to8} 32 vcvtps2pd zmm1{1to8}, [eax] 44 vaddps zmm2, zmm1, QWORD PTR [eax]{1to8} 46 vaddpd zmm2, zmm1, DWORD PTR [eax]{1to8}
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x86-64-inval-avx512f.s | 12 vcvtps2pd (%rax), %zmm1{1to8} 31 vcvtps2pd zmm1{1to8}, [rax] 42 vaddps zmm2, zmm1, QWORD PTR [rax]{1to8} 44 vaddpd zmm2, zmm1, DWORD PTR [rax]{1to8}
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avx512f.s | 16 vaddpd (%eax){1to8}, %zmm5, %zmm6 # AVX512F 21 vaddpd 1016(%edx){1to8}, %zmm5, %zmm6 # AVX512F Disp8 22 vaddpd 1024(%edx){1to8}, %zmm5, %zmm6 # AVX512F 23 vaddpd -1024(%edx){1to8}, %zmm5, %zmm6 # AVX512F Disp8 24 vaddpd -1032(%edx){1to8}, %zmm5, %zmm6 # AVX512F 92 vblendmpd (%eax){1to8}, %zmm5, %zmm6 # AVX512F 97 vblendmpd 1016(%edx){1to8}, %zmm5, %zmm6 # AVX512F Disp8 98 vblendmpd 1024(%edx){1to8}, %zmm5, %zmm6 # AVX512F 99 vblendmpd -1024(%edx){1to8}, %zmm5, %zmm6 # AVX512F Disp8 100 vblendmpd -1032(%edx){1to8}, %zmm5, %zmm6 # AVX512 [all...] |
inval-avx512f.l | 56 [ ]*12[ ]+vcvtps2pd \(%eax\), %zmm1\{1to8\} 76 [ ]*32[ ]+vcvtps2pd zmm1\{1to8\}, \[eax\] 88 [ ]*44[ ]+vaddps zmm2, zmm1, QWORD PTR \[eax\]\{1to8\} 90 [ ]*46[ ]+vaddpd zmm2, zmm1, DWORD PTR \[eax\]\{1to8\}
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x86-64-inval-avx512f.l | 54 [ ]*12[ ]+vcvtps2pd \(%rax\), %zmm1\{1to8\} 73 [ ]*31[ ]+vcvtps2pd zmm1\{1to8\}, \[rax\] 84 [ ]*42[ ]+vaddps zmm2, zmm1, QWORD PTR \[rax\]\{1to8\} 86 [ ]*44[ ]+vaddpd zmm2, zmm1, DWORD PTR \[rax\]\{1to8\}
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x86-64-avx512f.s | 16 vaddpd (%rcx){1to8}, %zmm29, %zmm30 # AVX512F 21 vaddpd 1016(%rdx){1to8}, %zmm29, %zmm30 # AVX512F Disp8 22 vaddpd 1024(%rdx){1to8}, %zmm29, %zmm30 # AVX512F 23 vaddpd -1024(%rdx){1to8}, %zmm29, %zmm30 # AVX512F Disp8 24 vaddpd -1032(%rdx){1to8}, %zmm29, %zmm30 # AVX512F 92 vblendmpd (%rcx){1to8}, %zmm29, %zmm30 # AVX512F 97 vblendmpd 1016(%rdx){1to8}, %zmm29, %zmm30 # AVX512F Disp8 98 vblendmpd 1024(%rdx){1to8}, %zmm29, %zmm30 # AVX512F 99 vblendmpd -1024(%rdx){1to8}, %zmm29, %zmm30 # AVX512F Disp8 100 vblendmpd -1032(%rdx){1to8}, %zmm29, %zmm30 # AVX512 [all...] |
avx512cd.d | 30 [ ]*[a-f0-9]+: 62 f2 fd 58 c4 30 vpconflictq \(%eax\)\{1to8\},%zmm6 35 [ ]*[a-f0-9]+: 62 f2 fd 58 c4 72 7f vpconflictq 0x3f8\(%edx\)\{1to8\},%zmm6 36 [ ]*[a-f0-9]+: 62 f2 fd 58 c4 b2 00 04 00 00 vpconflictq 0x400\(%edx\)\{1to8\},%zmm6 37 [ ]*[a-f0-9]+: 62 f2 fd 58 c4 72 80 vpconflictq -0x400\(%edx\)\{1to8\},%zmm6 38 [ ]*[a-f0-9]+: 62 f2 fd 58 c4 b2 f8 fb ff ff vpconflictq -0x408\(%edx\)\{1to8\},%zmm6 58 [ ]*[a-f0-9]+: 62 f2 fd 58 44 30 vplzcntq \(%eax\)\{1to8\},%zmm6 63 [ ]*[a-f0-9]+: 62 f2 fd 58 44 72 7f vplzcntq 0x3f8\(%edx\)\{1to8\},%zmm6 64 [ ]*[a-f0-9]+: 62 f2 fd 58 44 b2 00 04 00 00 vplzcntq 0x400\(%edx\)\{1to8\},%zmm6 65 [ ]*[a-f0-9]+: 62 f2 fd 58 44 72 80 vplzcntq -0x400\(%edx\)\{1to8\},%zmm6 66 [ ]*[a-f0-9]+: 62 f2 fd 58 44 b2 f8 fb ff ff vplzcntq -0x408\(%edx\)\{1to8\},%zmm [all...] |
avx512vbmi.s | 38 vpmultishiftqb (%eax){1to8}, %zmm5, %zmm6 # AVX512VBMI 43 vpmultishiftqb 1016(%edx){1to8}, %zmm5, %zmm6 # AVX512VBMI Disp8 44 vpmultishiftqb 1024(%edx){1to8}, %zmm5, %zmm6 # AVX512VBMI 45 vpmultishiftqb -1024(%edx){1to8}, %zmm5, %zmm6 # AVX512VBMI Disp8 46 vpmultishiftqb -1032(%edx){1to8}, %zmm5, %zmm6 # AVX512VBMI 81 vpmultishiftqb zmm6, zmm5, [eax]{1to8} # AVX512VBMI 86 vpmultishiftqb zmm6, zmm5, [edx+1016]{1to8} # AVX512VBMI Disp8 87 vpmultishiftqb zmm6, zmm5, [edx+1024]{1to8} # AVX512VBMI 88 vpmultishiftqb zmm6, zmm5, [edx-1024]{1to8} # AVX512VBMI Disp8 89 vpmultishiftqb zmm6, zmm5, [edx-1032]{1to8} # AVX512VBM [all...] |
x86-64-avx512cd-intel.d | 31 [ ]*[a-f0-9]+: 62 62 fd 58 c4 31 vpconflictq zmm30,QWORD PTR \[rcx\]\{1to8\} 36 [ ]*[a-f0-9]+: 62 62 fd 58 c4 72 7f vpconflictq zmm30,QWORD PTR \[rdx\+0x3f8\]\{1to8\} 37 [ ]*[a-f0-9]+: 62 62 fd 58 c4 b2 00 04 00 00 vpconflictq zmm30,QWORD PTR \[rdx\+0x400\]\{1to8\} 38 [ ]*[a-f0-9]+: 62 62 fd 58 c4 72 80 vpconflictq zmm30,QWORD PTR \[rdx-0x400\]\{1to8\} 39 [ ]*[a-f0-9]+: 62 62 fd 58 c4 b2 f8 fb ff ff vpconflictq zmm30,QWORD PTR \[rdx-0x408\]\{1to8\} 59 [ ]*[a-f0-9]+: 62 62 fd 58 44 31 vplzcntq zmm30,QWORD PTR \[rcx\]\{1to8\} 64 [ ]*[a-f0-9]+: 62 62 fd 58 44 72 7f vplzcntq zmm30,QWORD PTR \[rdx\+0x3f8\]\{1to8\} 65 [ ]*[a-f0-9]+: 62 62 fd 58 44 b2 00 04 00 00 vplzcntq zmm30,QWORD PTR \[rdx\+0x400\]\{1to8\} 66 [ ]*[a-f0-9]+: 62 62 fd 58 44 72 80 vplzcntq zmm30,QWORD PTR \[rdx-0x400\]\{1to8\} 67 [ ]*[a-f0-9]+: 62 62 fd 58 44 b2 f8 fb ff ff vplzcntq zmm30,QWORD PTR \[rdx-0x408\]\{1to8\} [all...] |
x86-64-avx512cd.d | 30 [ ]*[a-f0-9]+: 62 62 fd 58 c4 31 vpconflictq \(%rcx\)\{1to8\},%zmm30 35 [ ]*[a-f0-9]+: 62 62 fd 58 c4 72 7f vpconflictq 0x3f8\(%rdx\)\{1to8\},%zmm30 36 [ ]*[a-f0-9]+: 62 62 fd 58 c4 b2 00 04 00 00 vpconflictq 0x400\(%rdx\)\{1to8\},%zmm30 37 [ ]*[a-f0-9]+: 62 62 fd 58 c4 72 80 vpconflictq -0x400\(%rdx\)\{1to8\},%zmm30 38 [ ]*[a-f0-9]+: 62 62 fd 58 c4 b2 f8 fb ff ff vpconflictq -0x408\(%rdx\)\{1to8\},%zmm30 58 [ ]*[a-f0-9]+: 62 62 fd 58 44 31 vplzcntq \(%rcx\)\{1to8\},%zmm30 63 [ ]*[a-f0-9]+: 62 62 fd 58 44 72 7f vplzcntq 0x3f8\(%rdx\)\{1to8\},%zmm30 64 [ ]*[a-f0-9]+: 62 62 fd 58 44 b2 00 04 00 00 vplzcntq 0x400\(%rdx\)\{1to8\},%zmm30 65 [ ]*[a-f0-9]+: 62 62 fd 58 44 72 80 vplzcntq -0x400\(%rdx\)\{1to8\},%zmm30 66 [ ]*[a-f0-9]+: 62 62 fd 58 44 b2 f8 fb ff ff vplzcntq -0x408\(%rdx\)\{1to8\},%zmm3 [all...] |