| /external/llvm/test/MC/AArch64/ |
| neon-simd-shift.s | 388 uqrshrn2 v0.16b, v1.8h, #3
389 uqrshrn2 v0.8h, v1.4s, #3
390 uqrshrn2 v0.4s, v1.2d, #3
395 // CHECK: uqrshrn2 v0.16b, v1.8h, #3 // encoding: [0x20,0x9c,0x0d,0x6f]
396 // CHECK: uqrshrn2 v0.8h, v1.4s, #3 // encoding: [0x20,0x9c,0x1d,0x6f]
397 // CHECK: uqrshrn2 v0.4s, v1.2d, #3 // encoding: [0x20,0x9c,0x3d,0x6f]
|
| arm64-advsimd.s | [all...] |
| neon-diagnostics.s | [all...] |
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_advsimd_Blend.S | 300 uqrshrn2 v0.16b, v12.8h, #8
302 uqrshrn2 v1.16b, v13.8h, #8
304 uqrshrn2 v2.16b, v14.8h, #8
347 uqrshrn2 v0.16b, v12.8h, #8
349 uqrshrn2 v1.16b, v13.8h, #8
351 uqrshrn2 v2.16b, v14.8h, #8
|
| rsCpuIntrinsics_advsimd_3DLUT.S | 94 uqrshrn2 \dst, v14.8h, #8
96 uqrshrn2 \dst, v14.8h, #8
|
| rsCpuIntrinsics_advsimd_Blur.S | 230 uqrshrn2 v10.8h, v13.4s, #16 - FRACTION_BITS
233 uqrshrn2 v11.8h, v15.4s, #16 - FRACTION_BITS
330 uqrshrn2 v14.8h, v15.4s, #16
462 uqrshrn2 v14.8h, v15.4s, #16
660 uqrshrn2 v14.8h, v15.4s, #16
716 uqrshrn2 v14.8h, v15.4s, #16
800 uqrshrn2 v14.8h, v15.4s, #1
[all...] |
| /external/vixl/test/aarch64/ |
| test-trace-aarch64.cc | [all...] |
| /external/valgrind/none/tests/arm64/ |
| fp_and_simd.stdout.exp | [all...] |
| /external/vixl/src/aarch64/ |
| assembler-aarch64.h | [all...] |
| macro-assembler-aarch64.h | [all...] |
| simulator-aarch64.h | [all...] |
| simulator-aarch64.cc | [all...] |
| assembler-aarch64.cc | [all...] |
| logic-aarch64.cc | 2739 LogicVRegister Simulator::uqrshrn2(VectorFormat vform, function in class:vixl::aarch64::Simulator
[all...] |
