| /external/llvm/test/MC/AMDGPU/regression/ |
| bug28538.s | 8 v_mov_b32 v0, v0 row_bcast:0
12 v_mov_b32 v0, v0 row_bcast:13
|
| bug28413.s | 6 v_cmp_eq_i32 vcc, 0.5, v0
7 // SICI: v_cmp_eq_i32_e32 vcc, 0.5, v0 ; encoding: [0xf0,0x00,0x04,0x7d]
8 // VI: v_cmp_eq_i32_e32 vcc, 0.5, v0 ; encoding: [0xf0,0x00,0x84,0x7d]
14 v_cmp_eq_i32 vcc, 3.125, v0
15 // SICI: v_cmp_eq_i32_e32 vcc, 0x40480000, v0 ; encoding: [0xff,0x00,0x04,0x7d,0x00,0x00,0x48,0x40]
16 // VI: v_cmp_eq_i32_e32 vcc, 0x40480000, v0 ; encoding: [0xff,0x00,0x84,0x7d,0x00,0x00,0x48,0x40]
18 v_cmpx_eq_u32 vcc, 3.125, v0
19 // SICI: v_cmpx_eq_u32_e32 vcc, 0x40480000, v0 ; encoding: [0xff,0x00,0xa4,0x7d,0x00,0x00,0x48,0x40]
20 // VI: v_cmpx_eq_u32_e32 vcc, 0x40480000, v0 ; encoding: [0xff,0x00,0xb4,0x7d,0x00,0x00,0x48,0x40]
22 v_mov_b32 v0, 0.
[all...] |
| /external/llvm/test/MC/SystemZ/ |
| insn-bad-zEC12.s | 92 #CHECK: vab %v0, %v0, %v0
94 #CHECK: vaf %v0, %v0, %v0
96 #CHECK: vag %v0, %v0, %v0
98 #CHECK: vah %v0, %v0, %v
[all...] |
| insn-bad-z13.s | 23 #CHECK: vcdgb %v0, %v0, 0, -1
25 #CHECK: vcdgb %v0, %v0, 0, 16
27 #CHECK: vcdgb %v0, %v0, -1, 0
29 #CHECK: vcdgb %v0, %v0, 16, 0
31 vcdgb %v0, %v0, 0, -
[all...] |
| insn-good-z13.s | 21 #CHECK: vab %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xf3]
22 #CHECK: vab %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xf3]
23 #CHECK: vab %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xf3]
24 #CHECK: vab %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xf3]
27 vab %v0, %v0, %v
[all...] |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/ |
| advsimd-mov-bad.s | 2 mov x0, v0.D[0]
|
| neon-vfp-reglist.d | 8 0: 0c407000 ld1 {v0.8b}, \[x0\]
9 4: 0c40a000 ld1 {v0.8b, v1.8b}, \[x0\]
10 8: 0c406000 ld1 {v0.8b-v2.8b}, \[x0\]
11 c: 0c402000 ld1 {v0.8b-v3.8b}, \[x0\]
12 10: 0c408000 ld2 {v0.8b, v1.8b}, \[x0\]
13 14: 0c404000 ld3 {v0.8b-v2.8b}, \[x0\]
14 18: 0c400000 ld4 {v0.8b-v3.8b}, \[x0\]
15 1c: 0c007000 st1 {v0.8b}, \[x0\]
16 20: 0c00a000 st1 {v0.8b, v1.8b}, \[x0\]
17 24: 0c006000 st1 {v0.8b-v2.8b}, \[x0\
[all...] |
| /external/llvm/test/MC/AArch64/ |
| neon-shift-left-long.s | 8 sshll v0.8h, v1.8b, #3
9 sshll v0.4s, v1.4h, #3
10 sshll v0.2d, v1.2s, #3
11 sshll2 v0.8h, v1.16b, #3
12 sshll2 v0.4s, v1.8h, #3
13 sshll2 v0.2d, v1.4s, #3
15 // CHECK: sshll v0.8h, v1.8b, #3 // encoding: [0x20,0xa4,0x0b,0x0f]
16 // CHECK: sshll v0.4s, v1.4h, #3 // encoding: [0x20,0xa4,0x13,0x0f]
17 // CHECK: sshll v0.2d, v1.2s, #3 // encoding: [0x20,0xa4,0x23,0x0f]
18 // CHECK: sshll2 v0.8h, v1.16b, #3 // encoding: [0x20,0xa4,0x0b,0x4f
[all...] |
| arm64-advsimd.s | 5 abs.8b v0, v0
6 abs.16b v0, v0
7 abs.4h v0, v0
8 abs.8h v0, v0
9 abs.2s v0, v0
[all...] |
| neon-simd-shift.s | 8 sshr v0.8b, v1.8b, #3
9 sshr v0.4h, v1.4h, #3
10 sshr v0.2s, v1.2s, #3
11 sshr v0.16b, v1.16b, #3
12 sshr v0.8h, v1.8h, #3
13 sshr v0.4s, v1.4s, #3
14 sshr v0.2d, v1.2d, #3
15 // CHECK: sshr v0.8b, v1.8b, #3 // encoding: [0x20,0x04,0x0d,0x0f]
16 // CHECK: sshr v0.4h, v1.4h, #3 // encoding: [0x20,0x04,0x1d,0x0f]
17 // CHECK: sshr v0.2s, v1.2s, #3 // encoding: [0x20,0x04,0x3d,0x0f
[all...] |
| neon-sxtl.s | 8 sxtl v0.8h, v1.8b
9 sxtl v0.4s, v1.4h
10 sxtl v0.2d, v1.2s
12 // CHECK: sshll v0.8h, v1.8b, #0 // encoding: [0x20,0xa4,0x08,0x0f]
13 // CHECK: sshll v0.4s, v1.4h, #0 // encoding: [0x20,0xa4,0x10,0x0f]
14 // CHECK: sshll v0.2d, v1.2s, #0 // encoding: [0x20,0xa4,0x20,0x0f]
20 sxtl2 v0.8h, v1.16b
21 sxtl2 v0.4s, v1.8h
22 sxtl2 v0.2d, v1.4s
24 // CHECK: sshll2 v0.8h, v1.16b, #0 // encoding: [0x20,0xa4,0x08,0x4f
[all...] |
| neon-uxtl.s | 8 uxtl v0.8h, v1.8b
9 uxtl v0.4s, v1.4h
10 uxtl v0.2d, v1.2s
12 // CHECK: ushll v0.8h, v1.8b, #0 // encoding: [0x20,0xa4,0x08,0x2f]
13 // CHECK: ushll v0.4s, v1.4h, #0 // encoding: [0x20,0xa4,0x10,0x2f]
14 // CHECK: ushll v0.2d, v1.2s, #0 // encoding: [0x20,0xa4,0x20,0x2f]
20 uxtl2 v0.8h, v1.16b
21 uxtl2 v0.4s, v1.8h
22 uxtl2 v0.2d, v1.4s
24 // CHECK: ushll2 v0.8h, v1.16b, #0 // encoding: [0x20,0xa4,0x08,0x6f
[all...] |
| neon-bitwise-instructions.s | 8 and v0.8b, v1.8b, v2.8b
9 and v0.16b, v1.16b, v2.16b
11 // CHECK: and v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0x22,0x0e]
12 // CHECK: and v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0x22,0x4e]
18 orr v0.8b, v1.8b, v2.8b
19 orr v0.16b, v1.16b, v2.16b
21 // CHECK: orr v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0xa2,0x0e]
22 // CHECK: orr v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0xa2,0x4e]
28 eor v0.8b, v1.8b, v2.8b
29 eor v0.16b, v1.16b, v2.16
[all...] |
| neon-3vdiff.s | 17 saddl v0.8h, v1.8b, v2.8b
18 saddl v0.4s, v1.4h, v2.4h
19 saddl v0.2d, v1.2s, v2.2s
21 // CHECK: saddl v0.8h, v1.8b, v2.8b // encoding: [0x20,0x00,0x22,0x0e]
22 // CHECK: saddl v0.4s, v1.4h, v2.4h // encoding: [0x20,0x00,0x62,0x0e]
23 // CHECK: saddl v0.2d, v1.2s, v2.2s // encoding: [0x20,0x00,0xa2,0x0e]
25 saddl2 v0.4s, v1.8h, v2.8h
26 saddl2 v0.8h, v1.16b, v2.16b
27 saddl2 v0.2d, v1.4s, v2.4s
29 // CHECK: saddl2 v0.4s, v1.8h, v2.8h // encoding: [0x20,0x00,0x62,0x4e
[all...] |
| neon-mla-mls-instructions.s | 8 mla v0.8b, v1.8b, v2.8b
9 mla v0.16b, v1.16b, v2.16b
10 mla v0.4h, v1.4h, v2.4h
11 mla v0.8h, v1.8h, v2.8h
12 mla v0.2s, v1.2s, v2.2s
13 mla v0.4s, v1.4s, v2.4s
15 // CHECK: mla v0.8b, v1.8b, v2.8b // encoding: [0x20,0x94,0x22,0x0e]
16 // CHECK: mla v0.16b, v1.16b, v2.16b // encoding: [0x20,0x94,0x22,0x4e]
17 // CHECK: mla v0.4h, v1.4h, v2.4h // encoding: [0x20,0x94,0x62,0x0e]
18 // CHECK: mla v0.8h, v1.8h, v2.8h // encoding: [0x20,0x94,0x62,0x4e
[all...] |
| /frameworks/native/libs/math/tests/ |
| vec_test.cpp | 42 vec4 v0; local
43 EXPECT_EQ(v0.x, 0);
44 EXPECT_EQ(v0.y, 0);
45 EXPECT_EQ(v0.z, 0);
46 EXPECT_EQ(v0.w, 0);
86 vec4 v0(1, 2, 3, 4);
88 v0.x = 10;
89 v0.y = 20;
90 v0.z = 30;
91 v0.w = 40
[all...] |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/mips/ |
| ldstla-n64-shared.d | 11 0: 3c020123 lui v0,0x123
12 4: 34424567 ori v0,v0,0x4567
13 8: 00021438 dsll v0,v0,0x10
14 c: 344289ac ori v0,v0,0x89ac
15 10: 00021438 dsll v0,v0,0x10
16 14: 0043102d daddu v0,v0,v
[all...] |
| ldstla-n64.d | 11 0: 3c020123 lui v0,0x123
12 4: 34424567 ori v0,v0,0x4567
13 8: 00021438 dsll v0,v0,0x10
14 c: 344289ac ori v0,v0,0x89ac
15 10: 00021438 dsll v0,v0,0x10
16 14: 0043102d daddu v0,v0,v
[all...] |
| ldstla-32-mips3-shared.d | 11 [ 0-9a-f]+: dc82ffff ld v0,-1\(a0\)
12 [ 0-9a-f]+: 3c02abce lui v0,0xabce
13 [ 0-9a-f]+: 00441021 addu v0,v0,a0
14 [ 0-9a-f]+: dc42ef01 ld v0,-4351\(v0\)
15 [ 0-9a-f]+: 3c028000 lui v0,0x8000
16 [ 0-9a-f]+: 00441021 addu v0,v0,a0
17 [ 0-9a-f]+: dc420000 ld v0,0\(v0\
[all...] |
| ldstla-32-mips3.d | 11 [ 0-9a-f]+: dc82ffff ld v0,-1\(a0\)
12 [ 0-9a-f]+: 3c02abce lui v0,0xabce
13 [ 0-9a-f]+: 00441021 addu v0,v0,a0
14 [ 0-9a-f]+: dc42ef01 ld v0,-4351\(v0\)
15 [ 0-9a-f]+: 3c028000 lui v0,0x8000
16 [ 0-9a-f]+: 00441021 addu v0,v0,a0
17 [ 0-9a-f]+: dc420000 ld v0,0\(v0\
[all...] |
| xpa.d | 8 [0-9a-f]+ <[^>]*> 40420800 mfhc0 v0,c0_random
9 [0-9a-f]+ <[^>]*> 40428000 mfhc0 v0,c0_config
10 [0-9a-f]+ <[^>]*> 40420002 mfhc0 v0,c0_mvpconf0
11 [0-9a-f]+ <[^>]*> 40420007 mfhc0 v0,\$0,7
12 [0-9a-f]+ <[^>]*> 40c20800 mthc0 v0,c0_random
13 [0-9a-f]+ <[^>]*> 40c28000 mthc0 v0,c0_config
14 [0-9a-f]+ <[^>]*> 40c20002 mthc0 v0,c0_mvpconf0
15 [0-9a-f]+ <[^>]*> 40c20007 mthc0 v0,\$0,7
16 [0-9a-f]+ <[^>]*> 40620c00 mfhgc0 v0,c0_random
17 [0-9a-f]+ <[^>]*> 40628400 mfhgc0 v0,c0_confi
[all...] |
| /art/test/501-regression-packed-switch/smali/ |
| Test.smali | 22 packed-switch v0, :pswitch_data_6a
23 const/4 v0, 0x5
24 return v0
36 const/4 v0, 0x1
37 return v0
46 packed-switch v0, :pswitch_data
47 const/4 v0, 0x7
48 return v0
51 const/4 v0, 0x4
52 return v0
[all...] |
| /external/clang/test/Sema/ |
| 2010-05-31-palignr.c | 16 vSInt16 v0; local
17 v0 = *vdtbl;
18 v0 = _mm_alignr_epi8(v0, v0, i); // expected-error {{argument to '__builtin_ia32_palignr128' must be a constant integer}}
|
| /art/test/595-error-class/smali/ |
| merge.smali | 23 const/16 v0, 10
25 new-array v0, v0, [LAnError;
28 new-array v0, v0, [Ljava/lang/Integer;
30 return-object v0
|
| /external/libmpeg2/common/armv8/ |
| impeg2_mem_func.s | 86 //// Registers Used : v0
104 dup v0.8b, w1 ////x1 is the 8-bit value to be set into
106 st1 {v0.8b}, [x0], x2 ////Store the row 1
107 st1 {v0.8b}, [x0], x2 ////Store the row 2
108 st1 {v0.8b}, [x0], x2 ////Store the row 3
109 st1 {v0.8b}, [x0], x2 ////Store the row 4
110 st1 {v0.8b}, [x0], x2 ////Store the row 5
111 st1 {v0.8b}, [x0], x2 ////Store the row 6
112 st1 {v0.8b}, [x0], x2 ////Store the row 7
113 st1 {v0.8b}, [x0], x2 ////Store the row
[all...] |
