| /external/capstone/suite/MC/ARM/ |
| idiv.s.cs | 2 0x12,0xf3,0x11,0xe7 = sdiv r1, r2, r3
3 0x14,0xf5,0x33,0xe7 = udiv r3, r4, r5 package
|
| arm-shift-encoding.s.cs | 2 0x00,0x00,0x90,0xe7 = ldr r0, [r0, r0]
3 0x20,0x00,0x90,0xe7 = ldr r0, [r0, r0, lsr #32]
4 0x20,0x08,0x90,0xe7 = ldr r0, [r0, r0, lsr #16]
5 0x00,0x00,0x90,0xe7 = ldr r0, [r0, r0]
6 0x00,0x08,0x90,0xe7 = ldr r0, [r0, r0, lsl #16]
7 0x40,0x00,0x90,0xe7 = ldr r0, [r0, r0, asr #32]
8 0x40,0x08,0x90,0xe7 = ldr r0, [r0, r0, asr #16]
9 0x60,0x00,0x90,0xe7 = ldr r0, [r0, r0, rrx]
10 0x60,0x08,0x90,0xe7 = ldr r0, [r0, r0, ror #16]
20 0x00,0x00,0x80,0xe7 = str r0, [r0, r0
[all...] |
| /external/llvm/test/MC/SystemZ/ |
| insn-good-z13.s | 5 #CHECK: lcbb %r0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x27]
6 #CHECK: lcbb %r0, 0, 15 # encoding: [0xe7,0x00,0x00,0x00,0xf0,0x27]
7 #CHECK: lcbb %r0, 4095, 0 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x27]
8 #CHECK: lcbb %r0, 0(%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x27]
9 #CHECK: lcbb %r0, 0(%r15,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x27]
10 #CHECK: lcbb %r15, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x27]
11 #CHECK: lcbb %r2, 1383(%r3,%r4), 8 # encoding: [0xe7,0x23,0x45,0x67,0x80,0x27]
21 #CHECK: vab %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xf3]
22 #CHECK: vab %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xf3]
23 #CHECK: vab %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xf3
[all...] |
| /external/vixl/test/aarch32/traces/ |
| assembler-cond-rd-memop-rs-strb-a32.h | 62 0x03, 0x90, 0xc2, 0xe7 // strb al r9 r2 plus r3 Offset
74 0x0e, 0x90, 0xcd, 0xe7 // strb al r9 r13 plus r14 Offset
119 0x0c, 0x50, 0xc1, 0xe7 // strb al r5 r1 plus r12 Offset
128 0x00, 0x90, 0xcc, 0xe7 // strb al r9 r12 plus r0 Offset
149 0x0c, 0x10, 0xcb, 0xe7 // strb al r1 r11 plus r12 Offset
155 0x0d, 0x60, 0xc6, 0xe7 // strb al r6 r6 plus r13 Offset
272 0x03, 0x10, 0xc0, 0xe7 // strb al r1 r0 plus r3 Offset
281 0x0b, 0x20, 0xc6, 0xe7 // strb al r2 r6 plus r11 Offset
299 0x03, 0x50, 0xce, 0xe7 // strb al r5 r14 plus r3 Offset
329 0x0d, 0xd0, 0xcd, 0xe7 // strb al r13 r13 plus r13 Offse
[all...] |
| assembler-cond-rd-memop-rs-ldr-a32.h | 62 0x03, 0x90, 0x92, 0xe7 // ldr al r9 r2 plus r3 Offset
74 0x0e, 0x90, 0x9d, 0xe7 // ldr al r9 r13 plus r14 Offset
119 0x0c, 0x50, 0x91, 0xe7 // ldr al r5 r1 plus r12 Offset
128 0x00, 0x90, 0x9c, 0xe7 // ldr al r9 r12 plus r0 Offset
149 0x0c, 0x10, 0x9b, 0xe7 // ldr al r1 r11 plus r12 Offset
155 0x0d, 0x60, 0x96, 0xe7 // ldr al r6 r6 plus r13 Offset
272 0x03, 0x10, 0x90, 0xe7 // ldr al r1 r0 plus r3 Offset
281 0x0b, 0x20, 0x96, 0xe7 // ldr al r2 r6 plus r11 Offset
299 0x03, 0x50, 0x9e, 0xe7 // ldr al r5 r14 plus r3 Offset
329 0x0d, 0xd0, 0x9d, 0xe7 // ldr al r13 r13 plus r13 Offse
[all...] |
| assembler-cond-rd-memop-rs-ldrb-a32.h | 62 0x03, 0x90, 0xd2, 0xe7 // ldrb al r9 r2 plus r3 Offset
74 0x0e, 0x90, 0xdd, 0xe7 // ldrb al r9 r13 plus r14 Offset
119 0x0c, 0x50, 0xd1, 0xe7 // ldrb al r5 r1 plus r12 Offset
128 0x00, 0x90, 0xdc, 0xe7 // ldrb al r9 r12 plus r0 Offset
149 0x0c, 0x10, 0xdb, 0xe7 // ldrb al r1 r11 plus r12 Offset
155 0x0d, 0x60, 0xd6, 0xe7 // ldrb al r6 r6 plus r13 Offset
272 0x03, 0x10, 0xd0, 0xe7 // ldrb al r1 r0 plus r3 Offset
281 0x0b, 0x20, 0xd6, 0xe7 // ldrb al r2 r6 plus r11 Offset
299 0x03, 0x50, 0xde, 0xe7 // ldrb al r5 r14 plus r3 Offset
329 0x0d, 0xd0, 0xdd, 0xe7 // ldrb al r13 r13 plus r13 Offse
[all...] |
| assembler-cond-rd-memop-rs-str-a32.h | 62 0x03, 0x90, 0x82, 0xe7 // str al r9 r2 plus r3 Offset
74 0x0e, 0x90, 0x8d, 0xe7 // str al r9 r13 plus r14 Offset
119 0x0c, 0x50, 0x81, 0xe7 // str al r5 r1 plus r12 Offset
128 0x00, 0x90, 0x8c, 0xe7 // str al r9 r12 plus r0 Offset
149 0x0c, 0x10, 0x8b, 0xe7 // str al r1 r11 plus r12 Offset
155 0x0d, 0x60, 0x86, 0xe7 // str al r6 r6 plus r13 Offset
272 0x03, 0x10, 0x80, 0xe7 // str al r1 r0 plus r3 Offset
281 0x0b, 0x20, 0x86, 0xe7 // str al r2 r6 plus r11 Offset
299 0x03, 0x50, 0x8e, 0xe7 // str al r5 r14 plus r3 Offset
329 0x0d, 0xd0, 0x8d, 0xe7 // str al r13 r13 plus r13 Offse
[all...] |
| assembler-cond-rd-memop-rs-shift-amount-1to31-strb-a32.h | 62 0x83, 0x90, 0xc2, 0xe7 // strb al r9 r2 plus r3 LSL 1 Offset
74 0x8e, 0x90, 0xcd, 0xe7 // strb al r9 r13 plus r14 LSL 1 Offset
119 0x8c, 0x50, 0xc1, 0xe7 // strb al r5 r1 plus r12 LSL 1 Offset
128 0x80, 0x90, 0xcc, 0xe7 // strb al r9 r12 plus r0 LSL 1 Offset
149 0x8c, 0x10, 0xcb, 0xe7 // strb al r1 r11 plus r12 LSL 1 Offset
155 0x8d, 0x60, 0xc6, 0xe7 // strb al r6 r6 plus r13 LSL 1 Offset
272 0x83, 0x10, 0xc0, 0xe7 // strb al r1 r0 plus r3 LSL 1 Offset
281 0x8b, 0x20, 0xc6, 0xe7 // strb al r2 r6 plus r11 LSL 1 Offset
299 0x83, 0x50, 0xce, 0xe7 // strb al r5 r14 plus r3 LSL 1 Offset
329 0x8d, 0xd0, 0xcd, 0xe7 // strb al r13 r13 plus r13 LSL 1 Offse
[all...] |
| assembler-cond-rd-memop-rs-shift-amount-1to32-strb-a32.h | 62 0xa3, 0x90, 0xc2, 0xe7 // strb al r9 r2 plus r3 LSR 1 Offset
74 0xae, 0x90, 0xcd, 0xe7 // strb al r9 r13 plus r14 LSR 1 Offset
119 0xac, 0x50, 0xc1, 0xe7 // strb al r5 r1 plus r12 LSR 1 Offset
128 0xa0, 0x90, 0xcc, 0xe7 // strb al r9 r12 plus r0 LSR 1 Offset
149 0xac, 0x10, 0xcb, 0xe7 // strb al r1 r11 plus r12 LSR 1 Offset
155 0xad, 0x60, 0xc6, 0xe7 // strb al r6 r6 plus r13 LSR 1 Offset
272 0xa3, 0x10, 0xc0, 0xe7 // strb al r1 r0 plus r3 LSR 1 Offset
281 0xab, 0x20, 0xc6, 0xe7 // strb al r2 r6 plus r11 LSR 1 Offset
299 0xa3, 0x50, 0xce, 0xe7 // strb al r5 r14 plus r3 LSR 1 Offset
329 0xad, 0xd0, 0xcd, 0xe7 // strb al r13 r13 plus r13 LSR 1 Offse
[all...] |
| assembler-cond-rd-memop-rs-shift-amount-1to31-ldr-a32.h | 62 0x83, 0x90, 0x92, 0xe7 // ldr al r9 r2 plus r3 LSL 1 Offset
74 0x8e, 0x90, 0x9d, 0xe7 // ldr al r9 r13 plus r14 LSL 1 Offset
119 0x8c, 0x50, 0x91, 0xe7 // ldr al r5 r1 plus r12 LSL 1 Offset
128 0x80, 0x90, 0x9c, 0xe7 // ldr al r9 r12 plus r0 LSL 1 Offset
149 0x8c, 0x10, 0x9b, 0xe7 // ldr al r1 r11 plus r12 LSL 1 Offset
155 0x8d, 0x60, 0x96, 0xe7 // ldr al r6 r6 plus r13 LSL 1 Offset
272 0x83, 0x10, 0x90, 0xe7 // ldr al r1 r0 plus r3 LSL 1 Offset
281 0x8b, 0x20, 0x96, 0xe7 // ldr al r2 r6 plus r11 LSL 1 Offset
299 0x83, 0x50, 0x9e, 0xe7 // ldr al r5 r14 plus r3 LSL 1 Offset
329 0x8d, 0xd0, 0x9d, 0xe7 // ldr al r13 r13 plus r13 LSL 1 Offse
[all...] |
| assembler-cond-rd-memop-rs-shift-amount-1to31-ldrb-a32.h | 62 0x83, 0x90, 0xd2, 0xe7 // ldrb al r9 r2 plus r3 LSL 1 Offset
74 0x8e, 0x90, 0xdd, 0xe7 // ldrb al r9 r13 plus r14 LSL 1 Offset
119 0x8c, 0x50, 0xd1, 0xe7 // ldrb al r5 r1 plus r12 LSL 1 Offset
128 0x80, 0x90, 0xdc, 0xe7 // ldrb al r9 r12 plus r0 LSL 1 Offset
149 0x8c, 0x10, 0xdb, 0xe7 // ldrb al r1 r11 plus r12 LSL 1 Offset
155 0x8d, 0x60, 0xd6, 0xe7 // ldrb al r6 r6 plus r13 LSL 1 Offset
272 0x83, 0x10, 0xd0, 0xe7 // ldrb al r1 r0 plus r3 LSL 1 Offset
281 0x8b, 0x20, 0xd6, 0xe7 // ldrb al r2 r6 plus r11 LSL 1 Offset
299 0x83, 0x50, 0xde, 0xe7 // ldrb al r5 r14 plus r3 LSL 1 Offset
329 0x8d, 0xd0, 0xdd, 0xe7 // ldrb al r13 r13 plus r13 LSL 1 Offse
[all...] |
| assembler-cond-rd-memop-rs-shift-amount-1to31-str-a32.h | 62 0x83, 0x90, 0x82, 0xe7 // str al r9 r2 plus r3 LSL 1 Offset
74 0x8e, 0x90, 0x8d, 0xe7 // str al r9 r13 plus r14 LSL 1 Offset
119 0x8c, 0x50, 0x81, 0xe7 // str al r5 r1 plus r12 LSL 1 Offset
128 0x80, 0x90, 0x8c, 0xe7 // str al r9 r12 plus r0 LSL 1 Offset
149 0x8c, 0x10, 0x8b, 0xe7 // str al r1 r11 plus r12 LSL 1 Offset
155 0x8d, 0x60, 0x86, 0xe7 // str al r6 r6 plus r13 LSL 1 Offset
272 0x83, 0x10, 0x80, 0xe7 // str al r1 r0 plus r3 LSL 1 Offset
281 0x8b, 0x20, 0x86, 0xe7 // str al r2 r6 plus r11 LSL 1 Offset
299 0x83, 0x50, 0x8e, 0xe7 // str al r5 r14 plus r3 LSL 1 Offset
329 0x8d, 0xd0, 0x8d, 0xe7 // str al r13 r13 plus r13 LSL 1 Offse
[all...] |
| assembler-cond-rd-memop-rs-shift-amount-1to32-ldr-a32.h | 62 0xa3, 0x90, 0x92, 0xe7 // ldr al r9 r2 plus r3 LSR 1 Offset
74 0xae, 0x90, 0x9d, 0xe7 // ldr al r9 r13 plus r14 LSR 1 Offset
119 0xac, 0x50, 0x91, 0xe7 // ldr al r5 r1 plus r12 LSR 1 Offset
128 0xa0, 0x90, 0x9c, 0xe7 // ldr al r9 r12 plus r0 LSR 1 Offset
149 0xac, 0x10, 0x9b, 0xe7 // ldr al r1 r11 plus r12 LSR 1 Offset
155 0xad, 0x60, 0x96, 0xe7 // ldr al r6 r6 plus r13 LSR 1 Offset
272 0xa3, 0x10, 0x90, 0xe7 // ldr al r1 r0 plus r3 LSR 1 Offset
281 0xab, 0x20, 0x96, 0xe7 // ldr al r2 r6 plus r11 LSR 1 Offset
299 0xa3, 0x50, 0x9e, 0xe7 // ldr al r5 r14 plus r3 LSR 1 Offset
329 0xad, 0xd0, 0x9d, 0xe7 // ldr al r13 r13 plus r13 LSR 1 Offse
[all...] |
| assembler-cond-rd-memop-rs-shift-amount-1to32-ldrb-a32.h | 62 0xa3, 0x90, 0xd2, 0xe7 // ldrb al r9 r2 plus r3 LSR 1 Offset
74 0xae, 0x90, 0xdd, 0xe7 // ldrb al r9 r13 plus r14 LSR 1 Offset
119 0xac, 0x50, 0xd1, 0xe7 // ldrb al r5 r1 plus r12 LSR 1 Offset
128 0xa0, 0x90, 0xdc, 0xe7 // ldrb al r9 r12 plus r0 LSR 1 Offset
149 0xac, 0x10, 0xdb, 0xe7 // ldrb al r1 r11 plus r12 LSR 1 Offset
155 0xad, 0x60, 0xd6, 0xe7 // ldrb al r6 r6 plus r13 LSR 1 Offset
272 0xa3, 0x10, 0xd0, 0xe7 // ldrb al r1 r0 plus r3 LSR 1 Offset
281 0xab, 0x20, 0xd6, 0xe7 // ldrb al r2 r6 plus r11 LSR 1 Offset
299 0xa3, 0x50, 0xde, 0xe7 // ldrb al r5 r14 plus r3 LSR 1 Offset
329 0xad, 0xd0, 0xdd, 0xe7 // ldrb al r13 r13 plus r13 LSR 1 Offse
[all...] |
| assembler-cond-rd-memop-rs-shift-amount-1to32-str-a32.h | 62 0xa3, 0x90, 0x82, 0xe7 // str al r9 r2 plus r3 LSR 1 Offset
74 0xae, 0x90, 0x8d, 0xe7 // str al r9 r13 plus r14 LSR 1 Offset
119 0xac, 0x50, 0x81, 0xe7 // str al r5 r1 plus r12 LSR 1 Offset
128 0xa0, 0x90, 0x8c, 0xe7 // str al r9 r12 plus r0 LSR 1 Offset
149 0xac, 0x10, 0x8b, 0xe7 // str al r1 r11 plus r12 LSR 1 Offset
155 0xad, 0x60, 0x86, 0xe7 // str al r6 r6 plus r13 LSR 1 Offset
272 0xa3, 0x10, 0x80, 0xe7 // str al r1 r0 plus r3 LSR 1 Offset
281 0xab, 0x20, 0x86, 0xe7 // str al r2 r6 plus r11 LSR 1 Offset
299 0xa3, 0x50, 0x8e, 0xe7 // str al r5 r14 plus r3 LSR 1 Offset
329 0xad, 0xd0, 0x8d, 0xe7 // str al r13 r13 plus r13 LSR 1 Offse
[all...] |
| /device/linaro/bootloader/edk2/MdePkg/Include/Guid/ |
| FirmwareFileSystem3.h | 26 { 0x5473c07a, 0x3dcb, 0x4dca, { 0xbd, 0x6f, 0x1e, 0x96, 0x89, 0xe7, 0x34, 0x9a }}
|
| /libcore/luni/src/test/java/libcore/java/nio/charset/ |
| OldCharset_MultiByte_EUC_JP.java | 23 0xa4, 0xc8, 0xa4, 0xa6, 0xa4, 0xad, 0xa4, 0xe7, 0xa4, 0xa6, ' ',
24 0xa5, 0xc8, 0xa5, 0xa6, 0xa5, 0xad, 0xa5, 0xe7, 0xa5, 0xa6, ' ',
|
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Core/Dxe/ArchProtocol/Metronome/ |
| Metronome.h | 31 { 0x26baccb2, 0x6f42, 0x11d4, {0xbc, 0xe7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81} }
|
| /device/linaro/bootloader/edk2/MdePkg/Include/Protocol/ |
| Metronome.h | 24 { 0x26baccb2, 0x6f42, 0x11d4, {0xbc, 0xe7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } }
|
| /external/llvm/test/MC/ARM/ |
| udf-arm.s | 10 @ CHECK: udf #0 @ encoding: [0xf0,0x00,0xf0,0xe7]
|
| idiv.s | 15 @ A15-ARM: sdiv r1, r2, r3 @ encoding: [0x12,0xf3,0x11,0xe7]
16 @ A15-ARM: udiv r3, r4, r5 @ encoding: [0x14,0xf5,0x33,0xe7]
20 @ A15-ARM-NOTHUMBHWDIV: sdiv r1, r2, r3 @ encoding: [0x12,0xf3,0x11,0xe7]
21 @ A15-ARM-NOTHUMBHWDIV: udiv r3, r4, r5 @ encoding: [0x14,0xf5,0x33,0xe7]
25 @ ARMV8: sdiv r1, r2, r3 @ encoding: [0x12,0xf3,0x11,0xe7]
26 @ ARMV8: udiv r3, r4, r5 @ encoding: [0x14,0xf5,0x33,0xe7]
30 @ ARMV8-NOTHUMBHWDIV: sdiv r1, r2, r3 @ encoding: [0x12,0xf3,0x11,0xe7]
31 @ ARMV8-NOTHUMBHWDIV: udiv r3, r4, r5 @ encoding: [0x14,0xf5,0x33,0xe7]
|
| /external/capstone/suite/MC/Mips/ |
| micromips-expansions.s.cs | 5 0xe7,0x50,0x02,0x00 = ori $7, $7, 2
8 0xe7,0x50,0x02,0x00 = ori $7, $7, 2
11 0xe7,0x50,0x02,0x00 = ori $7, $7, 2
|
| mips-expansions.s.cs | 5 0x02,0x00,0xe7,0x34 = ori $7, $7, 2
8 0x02,0x00,0xe7,0x34 = ori $7, $7, 2
11 0x02,0x00,0xe7,0x34 = ori $7, $7, 2
|
| /device/linaro/bootloader/edk2/ArmPkg/Include/Ppi/ |
| ArmMpCoreInfo.h | 21 { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }
|
| /external/mp4parser/isoparser/src/main/java/com/googlecode/mp4parser/boxes/piff/ |
| PiffTrackEncryptionBox.java | 24 return new byte[]{(byte) 0x89, 0x74, (byte) 0xdb, (byte) 0xce, 0x7b, (byte) 0xe7, 0x4c, 0x51,
|
