| /external/llvm/examples/Kaleidoscope/MCJIT/cached/ |
| toy.cpp | 159 char Opcode;
162 UnaryExprAST(char opcode, ExprAST *operand)
163 : Opcode(opcode), Operand(operand) {}
1031 Function *F = TheHelper->getFunction(MakeLegalFunctionName(std::string("unary")+Opcode));
[all...] |
| /external/llvm/examples/Kaleidoscope/MCJIT/complete/ |
| toy.cpp | 178 char Opcode;
181 UnaryExprAST(char opcode, ExprAST *operand)
182 : Opcode(opcode), Operand(operand) {}
1102 MakeLegalFunctionName(std::string("unary") + Opcode));
[all...] |
| /external/llvm/examples/Kaleidoscope/MCJIT/initial/ |
| toy.cpp | 136 char Opcode;
139 UnaryExprAST(char opcode, ExprAST *operand)
140 : Opcode(opcode), Operand(operand) {}
889 Function *F = TheHelper->getFunction(MakeLegalFunctionName(std::string("unary")+Opcode));
[all...] |
| /external/llvm/examples/Kaleidoscope/MCJIT/lazy/ |
| toy.cpp | 138 char Opcode;
141 UnaryExprAST(char opcode, ExprAST *operand)
142 : Opcode(opcode), Operand(operand) {}
929 Function *F = TheHelper->getFunction(MakeLegalFunctionName(std::string("unary")+Opcode));
[all...] |
| /external/llvm/lib/Analysis/ |
| InstructionSimplify.cpp | 136 /// "(A op B) op' (A op C)". Here "op" is given by Opcode and "op'" is
140 static Value *ExpandBinOp(unsigned Opcode, Value *LHS, Value *RHS,
154 if (Value *L = SimplifyBinOp(Opcode, A, C, Q, MaxRecurse))
155 if (Value *R = SimplifyBinOp(Opcode, B, C, Q, MaxRecurse)) {
177 if (Value *L = SimplifyBinOp(Opcode, A, B, Q, MaxRecurse))
178 if (Value *R = SimplifyBinOp(Opcode, A, C, Q, MaxRecurse)) {
201 Instruction::BinaryOps Opcode = (Instruction::BinaryOps)Opc;
202 assert(Instruction::isAssociative(Opcode) && "Not an associative operation!");
212 if (Op0 && Op0->getOpcode() == Opcode) {
218 if (Value *V = SimplifyBinOp(Opcode, B, C, Q, MaxRecurse))
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 225 // opcode and that it has a immediate integer right operand.
256 // which lists [imm] as the list of opcode it's interested in, however
258 // here because the ComplexPattern opcode list is only used in
259 // root-level opcode matching.
286 // which lists [imm] as the list of opcode it's interested in, however
288 // here because the ComplexPattern opcode list is only used in
289 // root-level opcode matching.
778 assert(N.getOpcode() == ISD::SHL && "Invalid opcode.");
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelDAGToDAG.cpp | 149 SDNode *getS_BFE(unsigned Opcode, const SDLoc &DL, SDValue Val,
[all...] |
| R600ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMConstantIslandPass.cpp | 243 /// opcode.
[all...] |
| ARMFrameLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 246 unsigned Opcode = 0;
258 Opcode = IsValidInc ? Hexagon::L2_loadrub_pi : Hexagon::L2_loadrub_io;
260 Opcode = IsValidInc ? Hexagon::L2_loadrb_pi : Hexagon::L2_loadrb_io;
264 Opcode = IsValidInc ? Hexagon::L2_loadruh_pi : Hexagon::L2_loadruh_io;
266 Opcode = IsValidInc ? Hexagon::L2_loadrh_pi : Hexagon::L2_loadrh_io;
269 Opcode = IsValidInc ? Hexagon::L2_loadri_pi : Hexagon::L2_loadri_io;
272 Opcode = IsValidInc ? Hexagon::L2_loadrd_pi : Hexagon::L2_loadrd_io;
280 Opcode = IsValidInc ? Hexagon::V6_vL32b_pi : Hexagon::V6_vL32b_ai;
282 Opcode = IsValidInc ? Hexagon::V6_vL32Ub_pi : Hexagon::V6_vL32Ub_ai;
290 Opcode = IsValidInc ? Hexagon::V6_vL32b_pi_128
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | 264 llvm_unreachable("unexpected opcode");
424 unsigned Opcode = Instruction::UserOp1;
430 Opcode = I->getOpcode();
434 Opcode = C->getOpcode();
437 switch (Opcode) {
506 unsigned Opcode = Instruction::UserOp1;
512 Opcode = I->getOpcode();
516 Opcode = C->getOpcode();
520 switch (Opcode) {
[all...] |
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| PPCAsmParser.cpp | 274 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
841 int Opcode = Inst.getOpcode();
842 switch (Opcode) {
848 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
851 (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
927 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
941 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
955 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 320 unsigned Opcode = Instruction::UserOp1;
326 Opcode = I->getOpcode();
330 Opcode = C->getOpcode();
334 switch (Opcode) {
563 // Get the RR opcode corresponding to the RI one. FIXME: It would be
567 default: llvm_unreachable("Unexpected opcode!");
699 // Get the RR opcode corresponding to the RI one. FIXME: It would be
703 default: llvm_unreachable("Unexpected opcode!");
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 45 getTargetNodeName(unsigned Opcode) const
47 switch ((XCoreISD::NodeType)Opcode)
745 unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD :
748 SDValue Lo = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
752 SDValue Hi = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineAddSub.cpp | 341 unsigned Opcode = I->getOpcode();
343 if (Opcode == Instruction::FAdd || Opcode == Instruction::FSub) {
366 if (Opcode == Instruction::FSub)
[all...] |
| InstCombineAndOrXor.cpp | 67 /// This is the complement of getICmpCode, which turns an opcode and two
79 /// This is the complement of getFCmpCode, which turns an opcode and two
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| IndVarSimplify.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/MC/MCParser/ |
| AsmParser.cpp | 825 MCBinaryExpr::Opcode &Kind) {
908 MCBinaryExpr::Opcode Kind = MCBinaryExpr::Add;
924 MCBinaryExpr::Opcode Dummy;
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMFastISel.cpp | 712 unsigned Opcode = Instruction::UserOp1;
718 Opcode = I->getOpcode();
722 Opcode = C->getOpcode();
732 switch (Opcode) {
[all...] |
| ARMISelDAGToDAG.cpp | 209 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
217 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
225 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
232 /// should be 2, 3 or 4. The opcode array specifies the instructions used
305 // opcode and that it has a immediate integer right operand.
357 unsigned Opcode = MCID.getOpcode();
358 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
373 return TII->isFpMLxInstruction(Opcode);
726 unsigned Opcode = Op->getOpcode()
[all...] |
| ARMLoadStoreOptimizer.cpp | 91 int Offset, unsigned Base, bool BaseKill, int Opcode,
102 int Opcode,
109 int Opcode, unsigned Size,
132 static int getLoadStoreMultipleOpcode(int Opcode, ARM_AM::AMSubMode Mode) {
133 switch (Opcode) {
134 default: llvm_unreachable("Unhandled opcode!");
213 AMSubMode getLoadStoreMultipleSubMode(int Opcode) {
214 switch (Opcode) {
215 default: llvm_unreachable("Unhandled opcode!");
292 int Opcode, ARMCC::CondCodes Pred
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86FastISel.cpp | 178 // Get opcode and regclass of the output for the given load instruction.
236 // Get opcode and regclass of the output for the given store instruction.
308 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
327 unsigned Opcode = Instruction::UserOp1;
334 Opcode = I->getOpcode();
338 Opcode = C->getOpcode();
348 switch (Opcode) {
587 unsigned Opcode = Instruction::UserOp1;
589 Opcode = I->getOpcode();
592 Opcode = C->getOpcode()
[all...] |
| X86ISelDAGToDAG.cpp | [all...] |
