| /external/llvm/utils/TableGen/ |
| X86RecognizableInstr.h | 35 /// The opcode of the instruction, as used in an MCInst
43 /// The opcode field from the record; this is the opcode used in the Intel
45 uint8_t Opcode;
|
| /external/mesa3d/src/compiler/nir/ |
| nir_opcodes.py | 28 # Class that represents all the information we have about the opcode
31 class Opcode(object):
32 """Class that represents all the information we have about the opcode
39 - name is the name of the opcode (prepend nir_op_ for the enum name)
45 constant value of the opcode given the constant values of its inputs.
107 def opcode(name, output_size, output_type, input_sizes, input_types, function
110 opcodes[name] = Opcode(name, output_size, output_type, input_sizes,
114 opcode(name, 0, out_type, [0], [in_type], "", const_expr)
117 opcode(name, 0, ty, [0], [ty], "", const_expr)
121 opcode(name, output_size, output_type, [input_size], [input_type], ""
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_program_pair.h | 72 unsigned int Opcode:8;
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| MBlazeISelDAGToDAG.cpp | 190 unsigned Opcode = Node->getOpcode();
201 switch (Opcode) {
|
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 58 int Opcode = MI->getOpcode();
59 if (Opcode == XCore::LDWFI)
80 int Opcode = MI->getOpcode();
81 if (Opcode == XCore::STWFI)
129 /// the correspondent Branch instruction opcode.
142 /// opcode that matches the cc.
398 /// ReverseBranchCondition - Return the inverse opcode of the
|
| XCoreRegisterInfo.cpp | 147 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
148 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
152 int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
153 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
255 llvm_unreachable("Unexpected Opcode");
276 llvm_unreachable("Unexpected Opcode");
304 llvm_unreachable("Unexpected Opcode");
319 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
320 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
|
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| X86RecognizableInstr.h | 38 /// The opcode of the instruction, as used in an MCInst
44 /// The opcode field from the record; this is the opcode used in the Intel
46 uint8_t Opcode;
|
| /prebuilts/clang/host/darwin-x86/clang-4579689/include/llvm/CodeGen/GlobalISel/ |
| InstructionSelectorImpl.h | 130 unsigned Opcode = State.MIs[InsnID]->getOpcode();
132 << "], ExpectedOpcode=" << Expected << ") // Got=" << Opcode
135 if (Opcode != Expected) {
421 int64_t Opcode = MatchTable[CurrentIdx++];
426 State.MIs[0]->getDebugLoc(), TII.get(Opcode)));
428 << Opcode << ")\n");
|
| /prebuilts/clang/host/darwin-x86/clang-4630689/include/llvm/CodeGen/GlobalISel/ |
| InstructionSelectorImpl.h | 130 unsigned Opcode = State.MIs[InsnID]->getOpcode();
132 << "], ExpectedOpcode=" << Expected << ") // Got=" << Opcode
135 if (Opcode != Expected) {
421 int64_t Opcode = MatchTable[CurrentIdx++];
426 State.MIs[0]->getDebugLoc(), TII.get(Opcode)));
428 << Opcode << ")\n");
|
| /prebuilts/clang/host/darwin-x86/clang-4639204/include/llvm/CodeGen/GlobalISel/ |
| InstructionSelectorImpl.h | 130 unsigned Opcode = State.MIs[InsnID]->getOpcode();
132 << "], ExpectedOpcode=" << Expected << ") // Got=" << Opcode
135 if (Opcode != Expected) {
421 int64_t Opcode = MatchTable[CurrentIdx++];
426 State.MIs[0]->getDebugLoc(), TII.get(Opcode)));
428 << Opcode << ")\n");
|
| /prebuilts/clang/host/darwin-x86/clang-4691093/include/llvm/CodeGen/GlobalISel/ |
| InstructionSelectorImpl.h | 130 unsigned Opcode = State.MIs[InsnID]->getOpcode();
132 << "], ExpectedOpcode=" << Expected << ") // Got=" << Opcode
135 if (Opcode != Expected) {
421 int64_t Opcode = MatchTable[CurrentIdx++];
426 State.MIs[0]->getDebugLoc(), TII.get(Opcode)));
428 << Opcode << ")\n");
|
| /prebuilts/clang/host/linux-x86/clang-4579689/include/llvm/CodeGen/GlobalISel/ |
| InstructionSelectorImpl.h | 130 unsigned Opcode = State.MIs[InsnID]->getOpcode();
132 << "], ExpectedOpcode=" << Expected << ") // Got=" << Opcode
135 if (Opcode != Expected) {
421 int64_t Opcode = MatchTable[CurrentIdx++];
426 State.MIs[0]->getDebugLoc(), TII.get(Opcode)));
428 << Opcode << ")\n");
|
| /prebuilts/clang/host/linux-x86/clang-4630689/include/llvm/CodeGen/GlobalISel/ |
| InstructionSelectorImpl.h | 130 unsigned Opcode = State.MIs[InsnID]->getOpcode();
132 << "], ExpectedOpcode=" << Expected << ") // Got=" << Opcode
135 if (Opcode != Expected) {
421 int64_t Opcode = MatchTable[CurrentIdx++];
426 State.MIs[0]->getDebugLoc(), TII.get(Opcode)));
428 << Opcode << ")\n");
|
| /prebuilts/clang/host/linux-x86/clang-4639204/include/llvm/CodeGen/GlobalISel/ |
| InstructionSelectorImpl.h | 130 unsigned Opcode = State.MIs[InsnID]->getOpcode();
132 << "], ExpectedOpcode=" << Expected << ") // Got=" << Opcode
135 if (Opcode != Expected) {
421 int64_t Opcode = MatchTable[CurrentIdx++];
426 State.MIs[0]->getDebugLoc(), TII.get(Opcode)));
428 << Opcode << ")\n");
|
| /prebuilts/clang/host/linux-x86/clang-4691093/include/llvm/CodeGen/GlobalISel/ |
| InstructionSelectorImpl.h | 130 unsigned Opcode = State.MIs[InsnID]->getOpcode();
132 << "], ExpectedOpcode=" << Expected << ") // Got=" << Opcode
135 if (Opcode != Expected) {
421 int64_t Opcode = MatchTable[CurrentIdx++];
426 State.MIs[0]->getDebugLoc(), TII.get(Opcode)));
428 << Opcode << ")\n");
|
| /system/connectivity/wifilogd/ |
| protocol.h | 40 enum class Opcode : uint16_t {
54 Command& set_opcode(Opcode new_opcode) {
55 opcode = new_opcode;
69 Opcode opcode; member in struct:android::wifilogd::protocol::Command
72 // Payload follows, with content depending on |opcode|.
|
| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/ |
| Opcode.java | 42 public enum Opcode
44 NOP(0x00, "nop", ReferenceType.NONE, Format.Format10x, Opcode.CAN_CONTINUE),
45 MOVE(0x01, "move", ReferenceType.NONE, Format.Format12x, Opcode.CAN_CONTINUE | Opcode.SETS_REGISTER),
46 MOVE_FROM16(0x02, "move/from16", ReferenceType.NONE, Format.Format22x, Opcode.CAN_CONTINUE | Opcode.SETS_REGISTER),
47 MOVE_16(0x03, "move/16", ReferenceType.NONE, Format.Format32x, Opcode.CAN_CONTINUE | Opcode.SETS_REGISTER),
48 MOVE_WIDE(0x04, "move-wide", ReferenceType.NONE, Format.Format12x, Opcode.CAN_CONTINUE | Opcode.SETS_REGISTER | Opcode.SETS_WIDE_REGISTER)
[all...] |
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Efi/Protocol/DebugSupport/ |
| DebugSupport.h | 76 UINT16 Opcode;
186 UINT16 Opcode;
479 #define EXCEPT_EBC_INVALID_OPCODE 5 // opcode out of range
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Ufs/UfsBlockIoPei/ |
| UfsBlockIoPei.h | 145 UINT8 Opcode;
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/ |
| UfsPassThru.h | 128 UINT8 Opcode;
[all...] |
| /device/linaro/bootloader/edk2/MdeModulePkg/Universal/EbcDxe/EbcDebugger/ |
| EdbDisasmSupport.c | 1118 UINT8 Opcode;
1135 Opcode = GET_OPCODE(InstructionAddress);
1136 if ((Opcode < OPCODE_MAX) && (mEdbDisasmInstructionTable[Opcode] != NULL)) {
1137 InstructionLength = mEdbDisasmInstructionTable [Opcode] (InstructionAddress, SystemContext, &InstructionString);
1160 // Something wrong with OPCODE
1168 // Something wrong with OPCODE
|
| /device/linaro/bootloader/edk2/MdePkg/Include/Protocol/ |
| NvmExpressPassthru.h | 62 UINT32 Opcode:8;
|
| /external/capstone/ |
| MCInstrDesc.h | 124 unsigned short Opcode; // The opcode number
|
| /external/capstone/arch/X86/ |
| X86Disassembler.c | 171 uint32_t Opcode = MCInst_getOpcode(mcInst);
180 check_opcode = (Opcode != X86_INT);
182 check_opcode = ((Opcode != X86_BLENDPSrri &&
183 Opcode != X86_BLENDPDrri &&
184 Opcode != X86_PBLENDWrri &&
185 Opcode != X86_MPSADBWrri &&
186 Opcode != X86_DPPSrri &&
187 Opcode != X86_DPPDrri &&
188 Opcode != X86_INSERTPSrr &&
189 Opcode != X86_VBLENDPSYrri &
[all...] |
| /external/capstone/arch/XCore/ |
| XCoreDisassembler.c | 239 unsigned Opcode = fieldFromInstruction_4(Insn, 11, 5);
240 switch (Opcode) {
410 unsigned Opcode = fieldFromInstruction_4(Insn, 16, 4) |
412 switch (Opcode) {
648 unsigned Opcode;
652 Opcode = fieldFromInstruction_4(Insn, 27, 5);
653 switch (Opcode) {
|
